projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 120399ba YW |
1 | * Mediatek IOMMU Architecture Implementation |
| 2 | ||
| 7e42626a HZ |
3 | Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and |
| 4 | this M4U have two generations of HW architecture. Generation one uses flat | |
| 5 | pagetable, and only supports 4K size page mapping. Generation two uses the | |
| 6 | ARM Short-Descriptor translation table format for address translation. | |
| 120399ba YW |
7 | |
| 8 | About the M4U Hardware Block Diagram, please check below: | |
| 9 | ||
| 10 | EMI (External Memory Interface) | |
| 11 | | | |
| 12 | m4u (Multimedia Memory Management Unit) | |
| 13 | | | |
| 14 | SMI Common(Smart Multimedia Interface Common) | |
| 15 | | | |
| 16 | +----------------+------- | |
| 17 | | | | |
| 18 | | | | |
| 19 | SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). | |
| 20 | (display) (vdec) | |
| 21 | | | | |
| 22 | | | | |
| 23 | +-----+-----+ +----+----+ | |
| 24 | | | | | | | | |
| 25 | | | |... | | | ... There are different ports in each larb. | |
| 26 | | | | | | | | |
| 27 | OVL0 RDMA0 WDMA0 MC PP VLD | |
| 28 | ||
| 29 | As above, The Multimedia HW will go through SMI and M4U while it | |
| 30 | access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain | |
| 31 | smi local arbiter and smi common. It will control whether the Multimedia | |
| 32 | HW should go though the m4u for translation or bypass it and talk | |
| 33 | directly with EMI. And also SMI help control the power domain and clocks for | |
| 34 | each local arbiter. | |
| 35 | Normally we specify a local arbiter(larb) for each multimedia HW | |
| 36 | like display, video decode, and camera. And there are different ports | |
| 37 | in each larb. Take a example, There are many ports like MC, PP, VLD in the | |
| 38 | video decode local arbiter, all these ports are according to the video HW. | |
| 39 | ||
| 40 | Required properties: | |
| 7e42626a HZ |
41 | - compatible : must be one of the following string: |
| 42 | "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. | |
| 43 | "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. | |
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44 | - reg : m4u register base and size. |
| 45 | - interrupts : the interrupt of m4u. | |
| 46 | - clocks : must contain one entry for each clock-names. | |
| 47 | - clock-names : must be "bclk", It is the block clock of m4u. | |
| 48 | - mediatek,larbs : List of phandle to the local arbiters in the current Socs. | |
| 49 | Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort | |
| 50 | according to the local arbiter index, like larb0, larb1, larb2... | |
| 51 | - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. | |
| 52 | Specifies the mtk_m4u_id as defined in | |
| 7e42626a HZ |
53 | dt-binding/memory/mt2701-larb-port.h for mt2701 and |
| 54 | dt-binding/memory/mt8173-larb-port.h for mt8173 | |
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55 | |
| 56 | Example: | |
| 57 | iommu: iommu@10205000 { | |
| 58 | compatible = "mediatek,mt8173-m4u"; | |
| 59 | reg = <0 0x10205000 0 0x1000>; | |
| 60 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; | |
| 61 | clocks = <&infracfg CLK_INFRA_M4U>; | |
| 62 | clock-names = "bclk"; | |
| 63 | mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; | |
| 64 | #iommu-cells = <1>; | |
| 65 | }; | |
| 66 | ||
| 67 | Example for a client device: | |
| 68 | display { | |
| 69 | compatible = "mediatek,mt8173-disp"; | |
| 70 | iommus = <&iommu M4U_PORT_DISP_OVL0>, | |
| 71 | <&iommu M4U_PORT_DISP_RDMA0>; | |
| 72 | ... | |
| 73 | }; |