Commit | Line | Data |
---|---|---|
0760e8fa HD |
1 | NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) |
2 | ||
3 | Required properties: | |
4 | - compatible : "nvidia,tegra30-smmu" | |
5 | - reg : Should contain 3 register banks(address and length) for each | |
6 | of the SMMU register blocks. | |
7 | - interrupts : Should contain MC General interrupt. | |
8 | - nvidia,#asids : # of ASIDs | |
9 | - dma-window : IOVA start address and length. | |
10 | - nvidia,ahb : phandle to the ahb bus connected to SMMU. | |
11 | ||
12 | Example: | |
13 | smmu { | |
14 | compatible = "nvidia,tegra30-smmu"; | |
15 | reg = <0x7000f010 0x02c | |
16 | 0x7000f1f0 0x010 | |
17 | 0x7000f228 0x05c>; | |
18 | nvidia,#asids = <4>; /* # of ASIDs */ | |
19 | dma-window = <0 0x40000000>; /* IOVA start & length */ | |
20 | nvidia,ahb = <&ahb>; | |
21 | }; |