[deliverable/linux.git] / Documentation / devicetree / bindings / iommu / renesas,ipmmu-vmsa.txt

* Renesas VMSA-Compatible IOMMU

The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
It provides address translation for bus masters outside of the CPU, each
connected to the IPMMU through a port called micro-TLB.


Required Properties:

  - compatible: Must contain "renesas,ipmmu-vmsa".
  - reg: Base address and size of the IPMMU registers.
  - interrupts: Specifiers for the MMU fault interrupts. For instances that
    support secure mode two interrupts must be specified, for non-secure and
    secure mode, in that order. For instances that don't support secure mode a
    single interrupt must be specified.

  - #iommu-cells: Must be 1.

Each bus master connected to an IPMMU must reference the IPMMU in its device
node with the following property:

  - iommus: A reference to the IPMMU in two cells. The first cell is a phandle
    to the IPMMU and the second cell the number of the micro-TLB that the
    device is connected to.


Example: R8A7791 IPMMU-MX and VSP1-D0 bus master

	ipmmu_mx: mmu@fe951000 {
		compatible = "renasas,ipmmu-vmsa";
		reg = <0 0xfe951000 0 0x1000>;
		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
			     <0 221 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
	};

	vsp1@fe928000 {
		...
		iommus = <&ipmmu_mx 13>;
		...
	};
Commit	Line	Data
4a93f21d LP	1	* Renesas VMSA-Compatible IOMMU
	2
	3	The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
	4	It provides address translation for bus masters outside of the CPU, each
	5	connected to the IPMMU through a port called micro-TLB.
	6
	7
	8	Required Properties:
	9
	10	- compatible: Must contain "renesas,ipmmu-vmsa".
	11	- reg: Base address and size of the IPMMU registers.
	12	- interrupts: Specifiers for the MMU fault interrupts. For instances that
	13	support secure mode two interrupts must be specified, for non-secure and
	14	secure mode, in that order. For instances that don't support secure mode a
	15	single interrupt must be specified.
	16
	17	- #iommu-cells: Must be 1.
	18
	19	Each bus master connected to an IPMMU must reference the IPMMU in its device
	20	node with the following property:
	21
	22	- iommus: A reference to the IPMMU in two cells. The first cell is a phandle
	23	to the IPMMU and the second cell the number of the micro-TLB that the
	24	device is connected to.
	25
	26
	27	Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
	28
	29	ipmmu_mx: mmu@fe951000 {
	30	compatible = "renasas,ipmmu-vmsa";
	31	reg = <0 0xfe951000 0 0x1000>;
	32	interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
	33	<0 221 IRQ_TYPE_LEVEL_HIGH>;
	34	#iommu-cells = <1>;
	35	};
	36
	37	vsp1@fe928000 {
	38	...
	39	iommus = <&ipmmu_mx 13>;
	40	...
	41	};