Commit | Line | Data |
---|---|---|
92537d65 PD |
1 | SAMSUNG Exynos SoCs SROM Controller driver. |
2 | ||
3 | Required properties: | |
4 | - compatible : Should contain "samsung,exynos4210-srom". | |
5 | ||
6 | - reg: offset and length of the register set | |
7 | ||
8 | Optional properties: | |
9 | The SROM controller can be used to attach external peripherals. In this case | |
10 | extra properties, describing the bus behind it, should be specified as below: | |
11 | ||
12 | - #address-cells: Must be set to 2 to allow device address translation. | |
13 | Address is specified as (bank#, offset). | |
14 | ||
15 | - #size-cells: Must be set to 1 to allow device size passing | |
16 | ||
17 | - ranges: Must be set up to reflect the memory layout with four integer values | |
18 | per bank: | |
19 | <bank-number> 0 <parent address of bank> <size> | |
20 | ||
21 | Sub-nodes: | |
22 | The actual device nodes should be added as subnodes to the SROMc node. These | |
23 | subnodes, in addition to regular device specification, should contain the following | |
24 | properties, describing configuration of the relevant SROM bank: | |
25 | ||
26 | Required properties: | |
27 | - reg: bank number, base address (relative to start of the bank) and size of | |
28 | the memory mapped for the device. Note that base address will be | |
29 | typically 0 as this is the start of the bank. | |
30 | ||
31 | - samsung,srom-timing : array of 6 integers, specifying bank timings in the | |
32 | following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. | |
33 | Each value is specified in cycles and has the following | |
34 | meaning and valid range: | |
35 | Tacp : Page mode access cycle at Page mode (0 - 15) | |
36 | Tcah : Address holding time after CSn (0 - 15) | |
37 | Tcoh : Chip selection hold on OEn (0 - 15) | |
38 | Tacc : Access cycle (0 - 31, the actual time is N + 1) | |
39 | Tcos : Chip selection set-up before OEn (0 - 15) | |
40 | Tacs : Address set-up before CSn (0 - 15) | |
41 | ||
42 | Optional properties: | |
43 | - reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used. | |
44 | ||
45 | - samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured, | |
46 | else normal (1 data) page mode will be set. | |
47 | ||
48 | Example: basic definition, no banks are configured | |
49 | memory-controller@12570000 { | |
50 | compatible = "samsung,exynos4210-srom"; | |
51 | reg = <0x12570000 0x14>; | |
52 | }; | |
53 | ||
54 | Example: SROMc with SMSC911x ethernet chip on bank 3 | |
55 | memory-controller@12570000 { | |
56 | #address-cells = <2>; | |
57 | #size-cells = <1>; | |
58 | ranges = <0 0 0x04000000 0x20000 // Bank0 | |
59 | 1 0 0x05000000 0x20000 // Bank1 | |
60 | 2 0 0x06000000 0x20000 // Bank2 | |
61 | 3 0 0x07000000 0x20000>; // Bank3 | |
62 | ||
63 | compatible = "samsung,exynos4210-srom"; | |
64 | reg = <0x12570000 0x14>; | |
65 | ||
66 | ethernet@3,0 { | |
67 | compatible = "smsc,lan9115"; | |
68 | reg = <3 0 0x10000>; // Bank 3, offset = 0 | |
69 | phy-mode = "mii"; | |
70 | interrupt-parent = <&gpx0>; | |
71 | interrupts = <5 8>; | |
72 | reg-io-width = <2>; | |
73 | smsc,irq-push-pull; | |
74 | smsc,force-internal-phy; | |
75 | ||
76 | samsung,srom-page-mode; | |
77 | samsung,srom-timing = <9 12 1 9 1 1>; | |
78 | }; | |
79 | }; |