Commit | Line | Data |
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bc6b1e7b DM |
1 | Device tree bindings for OMAP general purpose memory controllers (GPMC) |
2 | ||
3 | The actual devices are instantiated from the child nodes of a GPMC node. | |
4 | ||
5 | Required properties: | |
6 | ||
7 | - compatible: Should be set to one of the following: | |
8 | ||
9 | ti,omap2420-gpmc (omap2420) | |
10 | ti,omap2430-gpmc (omap2430) | |
11 | ti,omap3430-gpmc (omap3430 & omap3630) | |
12 | ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) | |
13 | ti,am3352-gpmc (am335x devices) | |
14 | ||
15 | - reg: A resource specifier for the register space | |
16 | (see the example below) | |
17 | - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is | |
18 | completed. | |
19 | - #address-cells: Must be set to 2 to allow memory address translation | |
20 | - #size-cells: Must be set to 1 to allow CS address passing | |
21 | - gpmc,num-cs: The maximum number of chip-select lines that controller | |
22 | can support. | |
23 | - gpmc,num-waitpins: The maximum number of wait pins that controller can | |
24 | support. | |
25 | - ranges: Must be set up to reflect the memory layout with four | |
26 | integer values for each chip-select line in use: | |
27 | ||
28 | <cs-number> 0 <physical address of mapping> <size> | |
29 | ||
30 | Currently, calculated values derived from the contents | |
31 | of the per-CS register GPMC_CONFIG7 (as set up by the | |
32 | bootloader) are used for the physical address decoding. | |
33 | As this will change in the future, filling correct | |
34 | values here is a requirement. | |
384258f2 | 35 | - interrupt-controller: The GPMC driver implements and interrupt controller for |
b2bac25a RQ |
36 | the NAND events "fifoevent" and "termcount" plus the |
37 | rising/falling edges on the GPMC_WAIT pins. | |
384258f2 RQ |
38 | The interrupt number mapping is as follows |
39 | 0 - NAND_fifoevent | |
40 | 1 - NAND_termcount | |
b2bac25a RQ |
41 | 2 - GPMC_WAIT0 pin edge |
42 | 3 - GPMC_WAIT1 pin edge, and so on. | |
384258f2 | 43 | - interrupt-cells: Must be set to 2 |
d2d00862 RQ |
44 | - gpio-controller: The GPMC driver implements a GPIO controller for the |
45 | GPMC WAIT pins that can be used as general purpose inputs. | |
46 | 0 maps to GPMC_WAIT0 pin. | |
47 | - gpio-cells: Must be set to 2 | |
bc6b1e7b DM |
48 | |
49 | Timing properties for child nodes. All are optional and default to 0. | |
50 | ||
d36b4cd4 JH |
51 | - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds |
52 | ||
53 | Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: | |
54 | - gpmc,cs-on-ns: Assertion time | |
55 | - gpmc,cs-rd-off-ns: Read deassertion time | |
56 | - gpmc,cs-wr-off-ns: Write deassertion time | |
57 | ||
58 | ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: | |
59 | - gpmc,adv-on-ns: Assertion time | |
60 | - gpmc,adv-rd-off-ns: Read deassertion time | |
61 | - gpmc,adv-wr-off-ns: Write deassertion time | |
e116c054 NA |
62 | - gpmc,adv-aad-mux-on-ns: Assertion time for AAD |
63 | - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD | |
64 | - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD | |
d36b4cd4 JH |
65 | |
66 | WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: | |
67 | - gpmc,we-on-ns Assertion time | |
68 | - gpmc,we-off-ns: Deassertion time | |
69 | ||
70 | OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: | |
71 | - gpmc,oe-on-ns: Assertion time | |
72 | - gpmc,oe-off-ns: Deassertion time | |
e116c054 NA |
73 | - gpmc,oe-aad-mux-on-ns: Assertion time for AAD |
74 | - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD | |
d36b4cd4 JH |
75 | |
76 | Access time and cycle time timings (in nanoseconds) corresponding to | |
77 | GPMC_CONFIG5: | |
78 | - gpmc,page-burst-access-ns: Multiple access word delay | |
79 | - gpmc,access-ns: Start-cycle to first data valid delay | |
80 | - gpmc,rd-cycle-ns: Total read cycle time | |
81 | - gpmc,wr-cycle-ns: Total write cycle time | |
82 | - gpmc,bus-turnaround-ns: Turn-around time between successive accesses | |
83 | - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses | |
84 | - gpmc,clk-activation-ns: GPMC clock activation time | |
85 | - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid | |
86 | data | |
87 | ||
88 | Boolean timing parameters. If property is present parameter enabled and | |
89 | disabled if omitted: | |
90 | - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock | |
91 | - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock | |
92 | - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive | |
93 | accesses to a different CS | |
94 | - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive | |
95 | accesses to the same CS | |
96 | - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock | |
97 | - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock | |
98 | - gpmc,time-para-granularity: Multiply all access times by 2 | |
bc6b1e7b DM |
99 | |
100 | The following are only applicable to OMAP3+ and AM335x: | |
d36b4cd4 JH |
101 | - gpmc,wr-access-ns: In synchronous write mode, for single or |
102 | burst accesses, defines the number of | |
103 | GPMC_FCLK cycles from start access time | |
104 | to the GPMC_CLK rising edge used by the | |
105 | memory device for the first data capture. | |
106 | - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies | |
107 | the time when the first data is driven on | |
108 | the address-data bus. | |
bc6b1e7b | 109 | |
8c8a7771 JH |
110 | GPMC chip-select settings properties for child nodes. All are optional. |
111 | ||
112 | - gpmc,burst-length Page/burst length. Must be 4, 8 or 16. | |
113 | - gpmc,burst-wrap Enables wrap bursting | |
114 | - gpmc,burst-read Enables read page/burst mode | |
115 | - gpmc,burst-write Enables write page/burst mode | |
8c8a7771 JH |
116 | - gpmc,device-width Total width of device(s) connected to a GPMC |
117 | chip-select in bytes. The GPMC supports 8-bit | |
118 | and 16-bit devices and so this property must be | |
119 | 1 or 2. | |
120 | - gpmc,mux-add-data Address and data multiplexing configuration. | |
121 | Valid values are 1 for address-address-data | |
122 | multiplexing mode and 2 for address-data | |
123 | multiplexing mode. | |
124 | - gpmc,sync-read Enables synchronous read. Defaults to asynchronous | |
125 | is this is not set. | |
126 | - gpmc,sync-write Enables synchronous writes. Defaults to asynchronous | |
127 | is this is not set. | |
128 | - gpmc,wait-pin Wait-pin used by client. Must be less than | |
129 | "gpmc,num-waitpins". | |
130 | - gpmc,wait-on-read Enables wait monitoring on reads. | |
131 | - gpmc,wait-on-write Enables wait monitoring on writes. | |
bc6b1e7b DM |
132 | |
133 | Example for an AM33xx board: | |
134 | ||
135 | gpmc: gpmc@50000000 { | |
136 | compatible = "ti,am3352-gpmc"; | |
137 | ti,hwmods = "gpmc"; | |
138 | reg = <0x50000000 0x2000>; | |
139 | interrupts = <100>; | |
140 | ||
141 | gpmc,num-cs = <8>; | |
142 | gpmc,num-waitpins = <2>; | |
143 | #address-cells = <2>; | |
144 | #size-cells = <1>; | |
145 | ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ | |
384258f2 RQ |
146 | interrupt-controller; |
147 | #interrupt-cells = <2>; | |
d2d00862 RQ |
148 | gpio-controller; |
149 | #gpio-cells = <2>; | |
bc6b1e7b DM |
150 | |
151 | /* child nodes go here */ | |
152 | }; |