Commit | Line | Data |
---|---|---|
846deace KC |
1 | * Interrupt Controller |
2 | ||
3 | Properties: | |
4 | - compatible: "brcm,bcm3384-intc" | |
5 | ||
6 | Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs. | |
7 | ||
8 | - reg: Address/length pairs for each mask/status register set. Length must | |
9 | be 8. If multiple register sets are specified, the first set will | |
10 | handle IRQ offsets 0..31, the second set 32..63, and so on. | |
11 | ||
12 | - interrupt-controller: This is an interrupt controller. | |
13 | ||
14 | - #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge | |
15 | or polarity configuration is possible with this controller. | |
16 | ||
17 | - interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or | |
18 | from another INTC. | |
19 | ||
20 | - interrupts: The IRQ on the parent controller. | |
21 | ||
22 | Example: | |
23 | periph_intc: periph_intc@14e00038 { | |
24 | compatible = "brcm,bcm3384-intc"; | |
25 | ||
26 | /* | |
27 | * IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c | |
28 | * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344 | |
29 | */ | |
30 | reg = <0x14e00038 0x8 0x14e00340 0x8>; | |
31 | ||
32 | interrupt-controller; | |
33 | #interrupt-cells = <1>; | |
34 | ||
35 | interrupt-parent = <&cpu_intc>; | |
36 | interrupts = <4>; | |
37 | }; |