Commit | Line | Data |
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34bcda61 AV |
1 | * Freescale Enhanced Secure Digital Host Controller (eSDHC) |
2 | ||
3 | The Enhanced Secure Digital Host Controller provides an interface | |
4 | for MMC, SD, and SDIO types of memory cards. | |
5 | ||
6 | Required properties: | |
7 | - compatible : should be | |
40461472 | 8 | "fsl,<chip>-esdhc", "fsl,esdhc" |
34bcda61 AV |
9 | - reg : should contain eSDHC registers location and length. |
10 | - interrupts : should contain eSDHC interrupt. | |
11 | - interrupt-parent : interrupt source phandle. | |
12 | - clock-frequency : specifies eSDHC base clock frequency. | |
50dfe70f | 13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller |
7f217794 AB |
14 | reports inverted write-protect state; New devices should use |
15 | the generic "wp-inverted" property. | |
5fe23c7f | 16 | - sdhci,1-bit-only : (optional) specifies that a controller can |
7f217794 AB |
17 | only handle 1-bit data transfers. New devices should use the |
18 | generic "bus-width = <1>" property. | |
05e57eec RZ |
19 | - sdhci,auto-cmd12: (optional) specifies that a controller can |
20 | only handle auto CMD12. | |
34bcda61 AV |
21 | |
22 | Example: | |
23 | ||
24 | sdhci@2e000 { | |
40461472 | 25 | compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; |
34bcda61 AV |
26 | reg = <0x2e000 0x1000>; |
27 | interrupts = <42 0x8>; | |
28 | interrupt-parent = <&ipic>; | |
29 | /* Filled in by U-Boot */ | |
30 | clock-frequency = <0>; | |
31 | }; |