projects / deliverable / linux.git / blame
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1 | * Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX |
| 2 | ||
| 3 | The Enhanced Secure Digital Host Controller on Freescale i.MX family | |
| 4 | provides an interface for MMC, SD, and SDIO types of memory cards. | |
| 5 | ||
| 4efafee0 CB |
6 | This file documents differences between the core properties described |
| 7 | by mmc.txt and the properties used by the sdhci-esdhc-imx driver. | |
| 8 | ||
| abfafc2d | 9 | Required properties: |
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10 | - compatible : Should be "fsl,<chip>-esdhc", the supported chips include |
| 11 | "fsl,imx25-esdhc" | |
| 12 | "fsl,imx35-esdhc" | |
| 13 | "fsl,imx51-esdhc" | |
| 14 | "fsl,imx53-esdhc" | |
| 15 | "fsl,imx6q-usdhc" | |
| 16 | "fsl,imx6sl-usdhc" | |
| 17 | "fsl,imx6sx-usdhc" | |
| 2a2a7ea7 | 18 | "fsl,imx7d-usdhc" |
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19 | |
| 20 | Optional properties: | |
| a46d2619 | 21 | - fsl,wp-controller : Indicate to use controller internal write protection |
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22 | - fsl,delay-line : Specify the number of delay cells for override mode. |
| 23 | This is used to set the clock delay for DLL(Delay Line) on override mode | |
| 24 | to select a proper data sampling window in case the clock quality is not good | |
| 25 | due to signal path is too long on the board. Please refer to eSDHC/uSDHC | |
| 26 | chapter, DLL (Delay Line) section in RM for details. | |
| 07bf2b54 SH |
27 | - voltage-ranges : Specify the voltage range in case there are software |
| 28 | transparent level shifters on the outputs of the controller. Two cells are | |
| 29 | required, first cell specifies minimum slot voltage (mV), second cell | |
| 30 | specifies maximum slot voltage (mV). Several ranges could be specified. | |
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31 | - fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19 |
| 32 | in tuning procedure. | |
| 2a2a7ea7 HC |
33 | - fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. |
| 34 | The uSDHC use one delay cell as default increasing step to do tuning process. | |
| 35 | This property allows user to change the tuning step to more than one delay | |
| 36 | cells which is useful for some special boards or cards when the default | |
| 37 | tuning step can't find the proper delay window within limited tuning retries. | |
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38 | |
| 39 | Examples: | |
| 40 | ||
| 41 | esdhc@70004000 { | |
| 42 | compatible = "fsl,imx51-esdhc"; | |
| 43 | reg = <0x70004000 0x4000>; | |
| 44 | interrupts = <1>; | |
| a46d2619 | 45 | fsl,wp-controller; |
| abfafc2d SG |
46 | }; |
| 47 | ||
| 48 | esdhc@70008000 { | |
| 49 | compatible = "fsl,imx51-esdhc"; | |
| 50 | reg = <0x70008000 0x4000>; | |
| 51 | interrupts = <2>; | |
| 06693fcd FE |
52 | cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */ |
| 53 | wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */ | |
| abfafc2d | 54 | }; |