projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 036f29d5 ZG |
1 | * Hisilicon specific extensions to the Synopsys Designware Mobile |
| 2 | Storage Host Controller | |
| 3 | ||
| 4 | Read synopsys-dw-mshc.txt for more details | |
| 5 | ||
| 6 | The Synopsys designware mobile storage host controller is used to interface | |
| 7 | a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | |
| 8 | differences between the core Synopsys dw mshc controller properties described | |
| 9 | by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific | |
| 10 | extensions to the Synopsys Designware Mobile Storage Host Controller. | |
| 11 | ||
| 12 | Required Properties: | |
| 13 | ||
| 14 | * compatible: should be one of the following. | |
| c98be0c9 | 15 | - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions. |
| d9c7eb38 ZG |
16 | - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions. |
| 17 | ||
| 18 | Optional Properties: | |
| 19 | - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral. | |
| 036f29d5 | 20 | |
| 036f29d5 ZG |
21 | Example: |
| 22 | ||
| 23 | /* for Hi3620 */ | |
| 24 | ||
| 25 | /* SoC portion */ | |
| 26 | dwmmc_0: dwmmc0@fcd03000 { | |
| 27 | compatible = "hisilicon,hi4511-dw-mshc"; | |
| 28 | reg = <0xfcd03000 0x1000>; | |
| 29 | interrupts = <0 16 4>; | |
| 30 | #address-cells = <1>; | |
| 31 | #size-cells = <0>; | |
| 32 | clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>; | |
| 33 | clock-names = "ciu", "biu"; | |
| 036f29d5 ZG |
34 | }; |
| 35 | ||
| 36 | /* Board portion */ | |
| 37 | dwmmc0@fcd03000 { | |
| 38 | num-slots = <1>; | |
| 39 | vmmc-supply = <&ldo12>; | |
| 40 | fifo-depth = <0x100>; | |
| 036f29d5 ZG |
41 | pinctrl-names = "default"; |
| 42 | pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>; | |
| c83c8737 JC |
43 | bus-width = <4>; |
| 44 | disable-wp; | |
| 45 | cd-gpios = <&gpio10 3 0>; | |
| 46 | cap-mmc-highspeed; | |
| 47 | cap-sd-highspeed; | |
| 036f29d5 | 48 | }; |
| d9c7eb38 ZG |
49 | |
| 50 | /* for Hi6220 */ | |
| 51 | ||
| 52 | dwmmc_1: dwmmc1@f723e000 { | |
| 53 | compatible = "hisilicon,hi6220-dw-mshc"; | |
| 54 | num-slots = <0x1>; | |
| 55 | bus-width = <0x4>; | |
| 56 | disable-wp; | |
| 57 | cap-sd-highspeed; | |
| 58 | sd-uhs-sdr12; | |
| 59 | sd-uhs-sdr25; | |
| 60 | card-detect-delay = <200>; | |
| 61 | hisilicon,peripheral-syscon = <&ao_ctrl>; | |
| 62 | reg = <0x0 0xf723e000 0x0 0x1000>; | |
| 63 | interrupts = <0x0 0x49 0x4>; | |
| 64 | clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>; | |
| 65 | clock-names = "ciu", "biu"; | |
| 66 | cd-gpios = <&gpio1 0 1>; | |
| 67 | pinctrl-names = "default", "idle"; | |
| 68 | pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; | |
| 69 | pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; | |
| 70 | vqmmc-supply = <&ldo7>; | |
| 71 | vmmc-supply = <&ldo10>; | |
| 72 | }; |