Commit | Line | Data |
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b650352d CB |
1 | * Marvell sdhci-pxa v2/v3 controller |
2 | ||
3 | This file documents differences between the core properties in mmc.txt | |
4 | and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. | |
5 | ||
6 | Required properties: | |
5491ce3f MW |
7 | - compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or |
8 | "marvell,armada-380-sdhci". | |
9 | - reg: | |
10 | * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for | |
11 | the SDHCI registers. | |
d58a2ea5 GC |
12 | |
13 | * for "marvell,armada-380-sdhci", three register areas. The first | |
14 | one for the SDHCI registers themselves, the second one for the | |
15 | AXI/Mbus bridge registers of the SDHCI unit, the third one for the | |
16 | SDIO3 Configuration register | |
17 | - reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory | |
18 | for "marvell,armada-380-sdhci" | |
0654bb3c SH |
19 | - clocks: Array of clocks required for SDHCI; requires at least one for |
20 | I/O clock. | |
21 | - clock-names: Array of names corresponding to clocks property; shall be | |
22 | "io" for I/O clock and "core" for optional core clock. | |
b650352d CB |
23 | |
24 | Optional properties: | |
25 | - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. | |
26 | ||
27 | Example: | |
28 | ||
29 | sdhci@d4280800 { | |
30 | compatible = "mrvl,pxav3-mmc"; | |
31 | reg = <0xd4280800 0x800>; | |
32 | bus-width = <8>; | |
33 | interrupts = <27>; | |
0654bb3c SH |
34 | clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; |
35 | clock-names = "io", "core"; | |
b650352d CB |
36 | non-removable; |
37 | mrvl,clk-delay-cycles = <31>; | |
38 | }; | |
5491ce3f MW |
39 | |
40 | sdhci@d8000 { | |
41 | compatible = "marvell,armada-380-sdhci"; | |
d58a2ea5 GC |
42 | reg-names = "sdhci", "mbus", "conf-sdio3"; |
43 | reg = <0xd8000 0x1000>, | |
44 | <0xdc000 0x100>; | |
45 | <0x18454 0x4>; | |
5491ce3f MW |
46 | interrupts = <0 25 0x4>; |
47 | clocks = <&gateclk 17>; | |
0654bb3c | 48 | clock-names = "io"; |
5491ce3f MW |
49 | mrvl,clk-delay-cycles = <0x1F>; |
50 | }; |