[deliverable/linux.git] / Documentation / devicetree / bindings / mmc / sdhci-pxa.txt

* Marvell sdhci-pxa v2/v3 controller

This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.

Required properties:
- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
  "marvell,armada-380-sdhci".
- reg:
  * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
    the SDHCI registers.
  * for "marvell,armada-380-sdhci", two register areas. The first one
    for the SDHCI registers themselves, and the second one for the
    AXI/Mbus bridge registers of the SDHCI unit.
- clocks: Array of clocks required for SDHCI; requires at least one for
    I/O clock.
- clock-names: Array of names corresponding to clocks property; shall be
    "io" for I/O clock and "core" for optional core clock.

Optional properties:
- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.

Example:

sdhci@d4280800 {
	compatible = "mrvl,pxav3-mmc";
	reg = <0xd4280800 0x800>;
	bus-width = <8>;
	interrupts = <27>;
	clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
	clock-names = "io", "core";
	non-removable;
	mrvl,clk-delay-cycles = <31>;
};

sdhci@d8000 {
	compatible = "marvell,armada-380-sdhci";
	reg = <0xd8000 0x1000>, <0xdc000 0x100>;
	interrupts = <0 25 0x4>;
	clocks = <&gateclk 17>;
	clock-names = "io";
	mrvl,clk-delay-cycles = <0x1F>;
};
Commit	Line	Data
b650352d CB	1	* Marvell sdhci-pxa v2/v3 controller
	2
	3	This file documents differences between the core properties in mmc.txt
	4	and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
	5
	6	Required properties:
5491ce3f MW	7	- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
	8	"marvell,armada-380-sdhci".
	9	- reg:
	10	* for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
	11	the SDHCI registers.
	12	* for "marvell,armada-380-sdhci", two register areas. The first one
	13	for the SDHCI registers themselves, and the second one for the
	14	AXI/Mbus bridge registers of the SDHCI unit.
0654bb3c SH	15	- clocks: Array of clocks required for SDHCI; requires at least one for
	16	I/O clock.
	17	- clock-names: Array of names corresponding to clocks property; shall be
	18	"io" for I/O clock and "core" for optional core clock.
b650352d CB	19
	20	Optional properties:
	21	- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
	22
	23	Example:
	24
	25	sdhci@d4280800 {
	26	compatible = "mrvl,pxav3-mmc";
	27	reg = <0xd4280800 0x800>;
	28	bus-width = <8>;
	29	interrupts = <27>;
0654bb3c SH	30	clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
0654bb3c SH	31	clock-names = "io", "core";
b650352d CB	32	non-removable;
	33	mrvl,clk-delay-cycles = <31>;
	34	};
5491ce3f MW	35
	36	sdhci@d8000 {
	37	compatible = "marvell,armada-380-sdhci";
	38	reg = <0xd8000 0x1000>, <0xdc000 0x100>;
	39	interrupts = <0 25 0x4>;
	40	clocks = <&gateclk 17>;
0654bb3c	41	clock-names = "io";
5491ce3f MW	42	mrvl,clk-delay-cycles = <0x1F>;
5491ce3f MW	43	};