Commit | Line | Data |
---|---|---|
d6a01661 JCPV |
1 | Atmel NAND flash |
2 | ||
3 | Required properties: | |
51585778 | 4 | - compatible : should be "atmel,at91rm9200-nand" or "atmel,sama5d4-nand". |
d6a01661 | 5 | - reg : should specify localbus address and size used for the chip, |
a41b51a1 JW |
6 | and hardware ECC controller if available. |
7 | If the hardware ECC is PMECC, it should contain address and size for | |
abb1cd00 JW |
8 | PMECC and PMECC Error Location controller. |
9 | The PMECC lookup table address and size in ROM is optional. If not | |
10 | specified, driver will build it in runtime. | |
d6a01661 JCPV |
11 | - atmel,nand-addr-offset : offset for the address latch. |
12 | - atmel,nand-cmd-offset : offset for the command latch. | |
13 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | |
14 | representing partitions. | |
15 | ||
16 | - gpios : specifies the gpio pins to control the NAND device. detect is an | |
17 | optional gpio and may be set to 0 if not present. | |
18 | ||
19 | Optional properties: | |
1b719265 | 20 | - atmel,nand-has-dma : boolean to support dma transfer for nand read/write. |
d6a01661 JCPV |
21 | - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default. |
22 | Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first", | |
23 | "soft_bch". | |
a41b51a1 JW |
24 | - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware. |
25 | Only supported by at91sam9x5 or later sam9 product. | |
26 | - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC | |
27 | Controller. Supported values are: 2, 4, 8, 12, 24. | |
28 | - atmel,pmecc-sector-size : sector size for ECC computation. Supported values | |
29 | are: 512, 1024. | |
30 | - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM | |
31 | for different sector size. First one is for sector size 512, the next is for | |
abb1cd00 | 32 | sector size 1024. If not specified, driver will build the table in runtime. |
d6a01661 JCPV |
33 | - nand-bus-width : 8 or 16 bus width if not present 8 |
34 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | |
7dc37de7 JW |
35 | - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash |
36 | - Required properties: | |
37 | - compatible : "atmel,sama5d3-nfc". | |
38 | - reg : should specify the address and size used for NFC command registers, | |
39 | NFC registers and NFC Sram. NFC Sram address and size can be absent | |
40 | if don't want to use it. | |
2d405ec5 | 41 | - clocks: phandle to the peripheral clock |
6054d4d5 JW |
42 | - Optional properties: |
43 | - atmel,write-by-sram: boolean to enable NFC write by sram. | |
d6a01661 JCPV |
44 | |
45 | Examples: | |
46 | nand0: nand@40000000,0 { | |
47 | compatible = "atmel,at91rm9200-nand"; | |
48 | #address-cells = <1>; | |
49 | #size-cells = <1>; | |
50 | reg = <0x40000000 0x10000000 | |
51 | 0xffffe800 0x200 | |
52 | >; | |
c16524e6 NF |
53 | atmel,nand-addr-offset = <21>; /* ale */ |
54 | atmel,nand-cmd-offset = <22>; /* cle */ | |
d6a01661 JCPV |
55 | nand-on-flash-bbt; |
56 | nand-ecc-mode = "soft"; | |
c16524e6 NF |
57 | gpios = <&pioC 13 0 /* rdy */ |
58 | &pioC 14 0 /* nce */ | |
59 | 0 /* cd */ | |
d6a01661 JCPV |
60 | >; |
61 | partition@0 { | |
62 | ... | |
63 | }; | |
64 | }; | |
a41b51a1 JW |
65 | |
66 | /* for PMECC supported chips */ | |
67 | nand0: nand@40000000 { | |
68 | compatible = "atmel,at91rm9200-nand"; | |
69 | #address-cells = <1>; | |
70 | #size-cells = <1>; | |
71 | reg = < 0x40000000 0x10000000 /* bus addr & size */ | |
72 | 0xffffe000 0x00000600 /* PMECC addr & size */ | |
73 | 0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */ | |
74 | 0x00100000 0x00100000 /* ROM addr & size */ | |
75 | >; | |
76 | atmel,nand-addr-offset = <21>; /* ale */ | |
77 | atmel,nand-cmd-offset = <22>; /* cle */ | |
78 | nand-on-flash-bbt; | |
79 | nand-ecc-mode = "hw"; | |
80 | atmel,has-pmecc; /* enable PMECC */ | |
81 | atmel,pmecc-cap = <2>; | |
82 | atmel,pmecc-sector-size = <512>; | |
83 | atmel,pmecc-lookup-table-offset = <0x8000 0x10000>; | |
84 | gpios = <&pioD 5 0 /* rdy */ | |
85 | &pioD 4 0 /* nce */ | |
86 | 0 /* cd */ | |
87 | >; | |
88 | partition@0 { | |
89 | ... | |
90 | }; | |
91 | }; | |
7dc37de7 JW |
92 | |
93 | /* for NFC supported chips */ | |
94 | nand0: nand@40000000 { | |
95 | compatible = "atmel,at91rm9200-nand"; | |
96 | #address-cells = <1>; | |
97 | #size-cells = <1>; | |
98 | ranges; | |
99 | ... | |
100 | nfc@70000000 { | |
101 | compatible = "atmel,sama5d3-nfc"; | |
102 | #address-cells = <1>; | |
103 | #size-cells = <1>; | |
2d405ec5 | 104 | clocks = <&hsmc_clk> |
7dc37de7 JW |
105 | reg = < |
106 | 0x70000000 0x10000000 /* NFC Command Registers */ | |
107 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
108 | 0x00200000 0x00100000 /* NFC SRAM banks */ | |
109 | >; | |
110 | }; | |
111 | }; |