projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| bd1b40fe BN |
1 | * Broadcom STB NAND Controller |
| 2 | ||
| 3 | The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND | |
| 4 | flash chips. It has a memory-mapped register interface for both control | |
| 5 | registers and for its data input/output buffer. On some SoCs, this controller is | |
| 6 | paired with a custom DMA engine (inventively named "Flash DMA") which supports | |
| 7 | basic PROGRAM and READ functions, among other features. | |
| 8 | ||
| 9 | This controller was originally designed for STB SoCs (BCM7xxx) but is now | |
| 10 | available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and | |
| 11 | iProc/Cygnus. Its history includes several similar (but not fully register | |
| 12 | compatible) versions. | |
| 13 | ||
| 14 | Required properties: | |
| 15 | - compatible : should contain "brcm,brcmnand" and an appropriate version | |
| 16 | compatibility string, like "brcm,brcmnand-v7.0" | |
| 17 | Possible values: | |
| 18 | brcm,brcmnand-v4.0 | |
| 19 | brcm,brcmnand-v5.0 | |
| 20 | brcm,brcmnand-v6.0 | |
| 21 | brcm,brcmnand-v6.1 | |
| 22 | brcm,brcmnand-v7.0 | |
| 23 | brcm,brcmnand-v7.1 | |
| 24 | brcm,brcmnand | |
| 25 | - reg : the register start and length for NAND register region. | |
| 26 | (optional) Flash DMA register range (if present) | |
| 27 | (optional) NAND flash cache range (if at non-standard offset) | |
| 28 | - reg-names : a list of the names corresponding to the previous register | |
| 29 | ranges. Should contain "nand" and (optionally) | |
| 30 | "flash-dma" and/or "nand-cache". | |
| 31 | - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available) | |
| 32 | FLASH_DMA_DONE | |
| 33 | - interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" | |
| 34 | - interrupt-parent : See standard interrupt bindings | |
| 35 | - #address-cells : <1> - subnodes give the chip-select number | |
| 36 | - #size-cells : <0> | |
| 37 | ||
| 38 | Optional properties: | |
| 39 | - brcm,nand-has-wp : Some versions of this IP include a write-protect | |
| 40 | (WP) control bit. It is always available on >= | |
| 41 | v7.0. Use this property to describe the rare | |
| 42 | earlier versions of this core that include WP | |
| 43 | ||
| 44 | * NAND chip-select | |
| 45 | ||
| 46 | Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes | |
| 47 | to represent enabled chip-selects which (may) contain NAND flash chips. Their | |
| 48 | properties are as follows. | |
| 49 | ||
| 50 | Required properties: | |
| 51 | - compatible : should contain "brcm,nandcs" | |
| 52 | - reg : a single integer representing the chip-select | |
| 53 | number (e.g., 0, 1, 2, etc.) | |
| 54 | - #address-cells : see partition.txt | |
| 55 | - #size-cells : see partition.txt | |
| 56 | - nand-ecc-strength : see nand.txt | |
| 57 | - nand-ecc-step-size : must be 512 or 1024. See nand.txt | |
| 58 | ||
| 59 | Optional properties: | |
| 60 | - nand-on-flash-bbt : boolean, to enable the on-flash BBT for this | |
| 61 | chip-select. See nand.txt | |
| 62 | - brcm,nand-oob-sector-size : integer, to denote the spare area sector size | |
| 63 | expected for the ECC layout in use. This size, in | |
| 64 | addition to the strength and step-size, | |
| 65 | determines how the hardware BCH engine will lay | |
| 66 | out the parity bytes it stores on the flash. | |
| 67 | This property can be automatically determined by | |
| 68 | the flash geometry (particularly the NAND page | |
| 69 | and OOB size) in many cases, but when booting | |
| 70 | from NAND, the boot controller has only a limited | |
| 71 | number of available options for its default ECC | |
| 72 | layout. | |
| 73 | ||
| 74 | Each nandcs device node may optionally contain sub-nodes describing the flash | |
| 75 | partition mapping. See partition.txt for more detail. | |
| 76 | ||
| 77 | Example: | |
| 78 | ||
| 79 | nand@f0442800 { | |
| 80 | compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand"; | |
| 81 | reg = <0xF0442800 0x600>, | |
| 82 | <0xF0443000 0x100>; | |
| 83 | reg-names = "nand", "flash-dma"; | |
| 84 | interrupt-parent = <&hif_intr2_intc>; | |
| 85 | interrupts = <24>, <4>; | |
| 86 | ||
| 87 | #address-cells = <1>; | |
| 88 | #size-cells = <0>; | |
| 89 | ||
| 90 | nandcs@1 { | |
| 91 | compatible = "brcm,nandcs"; | |
| 92 | reg = <1>; // Chip select 1 | |
| 93 | nand-on-flash-bbt; | |
| 94 | nand-ecc-strength = <12>; | |
| 95 | nand-ecc-step-size = <512>; | |
| 96 | ||
| 97 | // Partitions | |
| 98 | #address-cells = <1>; // <2>, for 64-bit offset | |
| 99 | #size-cells = <1>; // <2>, for 64-bit length | |
| 100 | flash0.rootfs@0 { | |
| 101 | reg = <0 0x10000000>; | |
| 102 | }; | |
| 103 | flash0@0 { | |
| 104 | reg = <0 0>; // MTDPART_SIZ_FULL | |
| 105 | }; | |
| 106 | flash0.kernel@10000000 { | |
| 107 | reg = <0x10000000 0x400000>; | |
| 108 | }; | |
| 109 | }; | |
| 110 | }; |