Commit | Line | Data |
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bf9c37cb BC |
1 | * Serial NOR flash controller for MTK MT81xx (and similar) |
2 | ||
3 | Required properties: | |
4 | - compatible: should be "mediatek,mt8173-nor"; | |
5 | - reg: physical base address and length of the controller's register | |
6 | - clocks: the phandle of the clocks needed by the nor controller | |
7 | - clock-names: the names of the clocks | |
8 | the clocks should be named "spi" and "sf". "spi" is used for spi bus, | |
9 | and "sf" is used for controller, these are the clocks witch | |
10 | hardware needs to enabling nor flash and nor flash controller. | |
11 | See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. | |
12 | - #address-cells: should be <1> | |
13 | - #size-cells: should be <0> | |
14 | ||
15 | The SPI flash must be a child of the nor_flash node and must have a | |
16 | compatible property. Also see jedec,spi-nor.txt. | |
17 | ||
18 | Required properties: | |
19 | - compatible: May include a device-specific string consisting of the manufacturer | |
20 | and name of the chip. Must also include "jedec,spi-nor" for any | |
21 | SPI NOR flash that can be identified by the JEDEC READ ID opcode (0x9F). | |
22 | - reg : Chip-Select number | |
23 | ||
24 | Example: | |
25 | ||
26 | nor_flash: spi@1100d000 { | |
27 | compatible = "mediatek,mt8173-nor"; | |
28 | reg = <0 0x1100d000 0 0xe0>; | |
29 | clocks = <&pericfg CLK_PERI_SPI>, | |
30 | <&topckgen CLK_TOP_SPINFI_IFR_SEL>; | |
31 | clock-names = "spi", "sf"; | |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | status = "disabled"; | |
35 | ||
36 | flash@0 { | |
37 | compatible = "jedec,spi-nor"; | |
38 | reg = <0>; | |
39 | }; | |
40 | }; | |
41 |