Commit | Line | Data |
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d0fc2eaa KG |
1 | * MDIO IO device |
2 | ||
3 | The MDIO is a bus to which the PHY devices are connected. For each | |
4 | device that exists on this bus, a child node should be created. See | |
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5 | the definition of the PHY node in booting-without-of.txt for an example |
6 | of how to define a PHY. | |
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7 | |
8 | Required properties: | |
9 | - reg : Offset and length of the register set for the device | |
10 | - compatible : Should define the compatible device type for the | |
132d7bca SK |
11 | mdio. Currently supported strings/devices are: |
12 | - "fsl,gianfar-tbi" | |
13 | - "fsl,gianfar-mdio" | |
14 | - "fsl,etsec2-tbi" | |
15 | - "fsl,etsec2-mdio" | |
16 | - "fsl,ucc-mdio" | |
17 | - "fsl,fman-mdio" | |
18 | When device_type is "mdio", the following strings are also considered: | |
19 | - "gianfar" | |
20 | - "ucc_geth_phy" | |
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21 | |
22 | Example: | |
23 | ||
24 | mdio@24520 { | |
25 | reg = <24520 20>; | |
26 | compatible = "fsl,gianfar-mdio"; | |
27 | ||
28 | ethernet-phy@0 { | |
29 | ...... | |
30 | }; | |
31 | }; | |
32 | ||
b31a1d8b AF |
33 | * TBI Internal MDIO bus |
34 | ||
35 | As of this writing, every tsec is associated with an internal TBI PHY. | |
36 | This PHY is accessed through the local MDIO bus. These buses are defined | |
37 | similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". | |
38 | The TBI PHYs underneath them are similar to normal PHYs, but the reg property | |
39 | is considered instructive, rather than descriptive. The reg property should | |
40 | be chosen so it doesn't interfere with other PHYs on the bus. | |
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41 | |
42 | * Gianfar-compatible ethernet nodes | |
43 | ||
00262986 | 44 | Properties: |
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45 | |
46 | - device_type : Should be "network" | |
47 | - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" | |
48 | - compatible : Should be "gianfar" | |
49 | - reg : Offset and length of the register set for the device | |
00262986 SW |
50 | - interrupts : For FEC devices, the first interrupt is the device's |
51 | interrupt. For TSEC and eTSEC devices, the first interrupt is | |
52 | transmit, the second is receive, and the third is error. | |
e8f08ee0 | 53 | - phy-handle : See ethernet.txt file in the same directory. |
ae21888f | 54 | - fixed-link : See fixed-link.txt in the same directory. |
e8f08ee0 SS |
55 | - phy-connection-type : See ethernet.txt file in the same directory. |
56 | This property is only really needed if the connection is of type | |
57 | "rgmii-id", as all other connection types are detected by hardware. | |
00262986 SW |
58 | - fsl,magic-packet : If present, indicates that the hardware supports |
59 | waking up via magic packet. | |
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60 | - fsl,wake-on-filer : If present, indicates that the hardware supports |
61 | waking up by Filer General Purpose Interrupt (FGPI) asserted on the | |
62 | Rx int line. This is an advanced power management capability allowing | |
63 | certain packet types (user) defined by filer rules to wake up the system. | |
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64 | - bd-stash : If present, indicates that the hardware supports stashing |
65 | buffer descriptors in the L2. | |
66 | - rx-stash-len : Denotes the number of bytes of a received buffer to stash | |
67 | in the L2. | |
68 | - rx-stash-idx : Denotes the index of the first byte from the received | |
69 | buffer to stash in the L2. | |
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70 | |
71 | Example: | |
72 | ethernet@24000 { | |
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73 | device_type = "network"; |
74 | model = "TSEC"; | |
75 | compatible = "gianfar"; | |
00262986 SW |
76 | reg = <0x24000 0x1000>; |
77 | local-mac-address = [ 00 E0 0C 00 73 00 ]; | |
78 | interrupts = <29 2 30 2 34 2>; | |
79 | interrupt-parent = <&mpic>; | |
80 | phy-handle = <&phy0> | |
d0fc2eaa | 81 | }; |
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82 | |
83 | * Gianfar PTP clock nodes | |
84 | ||
85 | General Properties: | |
86 | ||
87 | - compatible Should be "fsl,etsec-ptp" | |
88 | - reg Offset and length of the register set for the device | |
89 | - interrupts There should be at least two interrupts. Some devices | |
90 | have as many as four PTP related interrupts. | |
91 | ||
92 | Clock Properties: | |
93 | ||
e58f6f4f | 94 | - fsl,cksel Timer reference clock source. |
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95 | - fsl,tclk-period Timer reference clock period in nanoseconds. |
96 | - fsl,tmr-prsc Prescaler, divides the output clock. | |
97 | - fsl,tmr-add Frequency compensation value. | |
98 | - fsl,tmr-fiper1 Fixed interval period pulse generator. | |
99 | - fsl,tmr-fiper2 Fixed interval period pulse generator. | |
100 | - fsl,max-adj Maximum frequency adjustment in parts per billion. | |
101 | ||
102 | These properties set the operational parameters for the PTP | |
103 | clock. You must choose these carefully for the clock to work right. | |
104 | Here is how to figure good values: | |
105 | ||
e58f6f4f | 106 | TimerOsc = selected reference clock MHz |
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107 | tclk_period = desired clock period nanoseconds |
108 | NominalFreq = 1000 / tclk_period MHz | |
109 | FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0) | |
110 | tmr_add = ceil(2^32 / FreqDivRatio) | |
111 | OutputClock = NominalFreq / tmr_prsc MHz | |
112 | PulseWidth = 1 / OutputClock microseconds | |
113 | FiperFreq1 = desired frequency in Hz | |
114 | FiperDiv1 = 1000000 * OutputClock / FiperFreq1 | |
115 | tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period | |
116 | max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1 | |
117 | ||
118 | The calculation for tmr_fiper2 is the same as for tmr_fiper1. The | |
119 | driver expects that tmr_fiper1 will be correctly set to produce a 1 | |
120 | Pulse Per Second (PPS) signal, since this will be offered to the PPS | |
121 | subsystem to synchronize the Linux clock. | |
122 | ||
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123 | Reference clock source is determined by the value, which is holded |
124 | in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the | |
125 | value, which will be directly written in those bits, that is why, | |
126 | according to reference manual, the next clock sources can be used: | |
127 | ||
128 | <0> - external high precision timer reference clock (TSEC_TMR_CLK | |
129 | input is used for this purpose); | |
130 | <1> - eTSEC system clock; | |
131 | <2> - eTSEC1 transmit clock; | |
132 | <3> - RTC clock input. | |
133 | ||
134 | When this attribute is not used, eTSEC system clock will serve as | |
135 | IEEE 1588 timer reference clock. | |
136 | ||
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137 | Example: |
138 | ||
139 | ptp_clock@24E00 { | |
140 | compatible = "fsl,etsec-ptp"; | |
141 | reg = <0x24E00 0xB0>; | |
142 | interrupts = <12 0x8 13 0x8>; | |
143 | interrupt-parent = < &ipic >; | |
e58f6f4f | 144 | fsl,cksel = <1>; |
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145 | fsl,tclk-period = <10>; |
146 | fsl,tmr-prsc = <100>; | |
147 | fsl,tmr-add = <0x999999A4>; | |
148 | fsl,tmr-fiper1 = <0x3B9AC9F6>; | |
149 | fsl,tmr-fiper2 = <0x00018696>; | |
150 | fsl,max-adj = <659999998>; | |
151 | }; |