projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 53126a2f | 1 | * Synopsys Designware PCIe interface |
| 340cba60 JH |
2 | |
| 3 | Required properties: | |
| 4 | - compatible: should contain "snps,dw-pcie" to identify the | |
| 5 | core, plus an identifier for the specific instance, such | |
| 6 | as "samsung,exynos5440-pcie". | |
| 7 | - reg: base addresses and lengths of the pcie controller, | |
| 8 | the phy controller, additional register for the phy controller. | |
| 9 | - interrupts: interrupt values for level interrupt, | |
| 10 | pulse interrupt, special interrupt. | |
| 11 | - clocks: from common clock binding: handle to pci clock. | |
| 12 | - clock-names: from common clock binding: should be "pcie" and "pcie_bus". | |
| 13 | - #address-cells: set to <3> | |
| 14 | - #size-cells: set to <2> | |
| 15 | - device_type: set to "pci" | |
| 16 | - ranges: ranges for the PCI memory and I/O regions | |
| 17 | - #interrupt-cells: set to <1> | |
| 18 | - interrupt-map-mask and interrupt-map: standard PCI properties | |
| 19 | to define the mapping of the PCIe interface to interrupt | |
| 20 | numbers. | |
| 4b1ced84 | 21 | - num-lanes: number of lanes to use |
| 340cba60 JH |
22 | - reset-gpio: gpio pin number of power good signal |
| 23 | ||
| 24 | Example: | |
| 25 | ||
| 26 | SoC specific DT Entry: | |
| 27 | ||
| 28 | pcie@290000 { | |
| 29 | compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; | |
| 30 | reg = <0x290000 0x1000 | |
| 31 | 0x270000 0x1000 | |
| 32 | 0x271000 0x40>; | |
| 33 | interrupts = <0 20 0>, <0 21 0>, <0 22 0>; | |
| 34 | clocks = <&clock 28>, <&clock 27>; | |
| 35 | clock-names = "pcie", "pcie_bus"; | |
| 36 | #address-cells = <3>; | |
| 37 | #size-cells = <2>; | |
| 38 | device_type = "pci"; | |
| 39 | ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ | |
| 40 | 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ | |
| 41 | 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ | |
| 42 | #interrupt-cells = <1>; | |
| 43 | interrupt-map-mask = <0 0 0 0>; | |
| 44 | interrupt-map = <0x0 0 &gic 53>; | |
| 4b1ced84 | 45 | num-lanes = <4>; |
| 340cba60 JH |
46 | }; |
| 47 | ||
| 48 | pcie@2a0000 { | |
| 49 | compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; | |
| 50 | reg = <0x2a0000 0x1000 | |
| 51 | 0x272000 0x1000 | |
| 52 | 0x271040 0x40>; | |
| 53 | interrupts = <0 23 0>, <0 24 0>, <0 25 0>; | |
| 54 | clocks = <&clock 29>, <&clock 27>; | |
| 55 | clock-names = "pcie", "pcie_bus"; | |
| 56 | #address-cells = <3>; | |
| 57 | #size-cells = <2>; | |
| 58 | device_type = "pci"; | |
| 59 | ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ | |
| 60 | 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ | |
| 61 | 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ | |
| 62 | #interrupt-cells = <1>; | |
| 63 | interrupt-map-mask = <0 0 0 0>; | |
| 64 | interrupt-map = <0x0 0 &gic 56>; | |
| 4b1ced84 | 65 | num-lanes = <4>; |
| 340cba60 JH |
66 | }; |
| 67 | ||
| 68 | Board specific DT Entry: | |
| 69 | ||
| 70 | pcie@290000 { | |
| 71 | reset-gpio = <&pin_ctrl 5 0>; | |
| 72 | }; | |
| 73 | ||
| 74 | pcie@2a0000 { | |
| 75 | reset-gpio = <&pin_ctrl 22 0>; | |
| 76 | }; |