Commit | Line | Data |
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1db823ee LS |
1 | * Freescale i.MX6 PCIe interface |
2 | ||
3 | This PCIe host controller is based on the Synopsis Designware PCIe IP | |
4 | and thus inherits all the common properties defined in designware-pcie.txt. | |
5 | ||
6 | Required properties: | |
7 | - compatible: "fsl,imx6q-pcie" | |
8 | - reg: base addresse and length of the pcie controller | |
9 | - interrupts: A list of interrupt outputs of the controller. Must contain an | |
10 | entry for each entry in the interrupt-names property. | |
11 | - interrupt-names: Must include the following entries: | |
12 | - "msi": The interrupt that is asserted when an MSI is received | |
13 | - clock-names: Must include the following additional entries: | |
14 | - "pcie_phy" | |
15 | ||
28e3abe5 JW |
16 | Optional properties: |
17 | - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0 | |
18 | - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0 | |
19 | - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 | |
20 | - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127 | |
21 | - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127 | |
22 | ||
1db823ee LS |
23 | Example: |
24 | ||
25 | pcie@0x01000000 { | |
26 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | |
fcd17303 LS |
27 | reg = <0x01ffc000 0x04000>, |
28 | <0x01f00000 0x80000>; | |
29 | reg-names = "dbi", "config"; | |
1db823ee LS |
30 | #address-cells = <3>; |
31 | #size-cells = <2>; | |
32 | device_type = "pci"; | |
33 | ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 | |
34 | 0x81000000 0 0 0x01f80000 0 0x00010000 | |
35 | 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; | |
36 | num-lanes = <1>; | |
37 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
38 | interrupt-names = "msi"; | |
39 | #interrupt-cells = <1>; | |
40 | interrupt-map-mask = <0 0 0 0x7>; | |
41 | interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
42 | <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
43 | <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
44 | <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; | |
45 | clocks = <&clks 144>, <&clks 206>, <&clks 189>; | |
46 | clock-names = "pcie", "pcie_bus", "pcie_phy"; | |
47 | }; |