[deliverable/linux.git] / Documentation / devicetree / bindings / pci / mvebu-pci.txt

* Marvell EBU PCIe interfaces

Mandatory properties:

- compatible: one of the following values:
    marvell,armada-370-pcie
    marvell,armada-xp-pcie
    marvell,kirkwood-pcie
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- bus-range: PCI bus numbers covered
- device_type, set to "pci"
- ranges: ranges describing the MMIO registers to control the PCIe
  interfaces, and ranges describing the MBus windows needed to access
  the memory and I/O regions of each PCIe interface.
- msi-parent: Link to the hardware entity that serves as the Message
  Signaled Interrupt controller for this PCI controller.

The ranges describing the MMIO registers have the following layout:

    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s

where:

  * r is a 32-bits value that gives the offset of the MMIO
  registers of this PCIe interface, from the base of the internal
  registers.

  * s is a 32-bits value that give the size of this MMIO
  registers area. This range entry translates the '0x82000000 0 r' PCI
  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  of the internal register window (as identified by MBUS_ID(0xf0,
  0x01)).

The ranges describing the MBus windows have the following layout:

    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0

where:

   * t is the type of the MBus window (as defined by the standard PCI DT
   bindings), 1 for I/O and 2 for memory.

   * s is the PCI slot that corresponds to this PCIe interface

   * w is the 'target ID' value for the MBus window

   * a the 'attribute' value for the MBus window.

Since the location and size of the different MBus windows is not fixed in
hardware, and only determined in runtime, those ranges cover the full first
4 GB of the physical address space, and do not translate into a valid CPU
address.

In addition, the device tree node must have sub-nodes describing each
PCIe interface, having the following mandatory properties:

- reg: used only for interrupt mapping, so only the first four bytes
  are used to refer to the correct bus number and device number.
- assigned-addresses: reference to the MMIO registers used to control
  this PCIe interface.
- clocks: the clock associated to this PCIe interface
- marvell,pcie-port: the physical PCIe port number
- status: either "disabled" or "okay"
- device_type, set to "pci"
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- ranges, translating the MBus windows ranges of the parent node into
  standard PCI addresses.
- interrupt-map-mask and interrupt-map, standard PCI properties to
  define the mapping of the PCIe interface to interrupt numbers.

and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
  multiple lanes. If this property is not found, we assume that the
  value is 0.
- reset-gpios: optional gpio to PERST#
- reset-delay-us: delay in us to wait after reset de-assertion

Example:

pcie-controller {
	compatible = "marvell,armada-xp-pcie";
	status = "disabled";
	device_type = "pci";

	#address-cells = <3>;
	#size-cells = <2>;

	bus-range = <0x00 0xff>;
	msi-parent = <&mpic>;

	ranges =
	       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000	/* Port 0.0 registers */
		0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000	/* Port 2.0 registers */
		0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000	/* Port 0.1 registers */
		0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000	/* Port 0.2 registers */
		0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000	/* Port 0.3 registers */
		0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000	/* Port 1.0 registers */
		0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000	/* Port 3.0 registers */
		0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000	/* Port 1.1 registers */
		0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000	/* Port 1.2 registers */
		0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000	/* Port 1.3 registers */
		0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
		0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
		0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
		0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
		0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
		0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
		0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
		0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

		0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
		0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
		0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
		0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
		0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
		0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
		0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
		0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

		0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
		0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */

		0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
		0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;

	pcie@1,0 {
		device_type = "pci";
		assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
		reg = <0x0800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
			  0x81000000 0 0 0x81000000 0x1 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 58>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <0>;
		/* low-active PERST# reset on GPIO 25 */
		reset-gpios = <&gpio0 25 1>;
		/* wait 20ms for device settle after reset deassertion */
		reset-delay-us = <20000>;
		clocks = <&gateclk 5>;
		status = "disabled";
	};

	pcie@2,0 {
		device_type = "pci";
		assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
		reg = <0x1000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
			  0x81000000 0 0 0x81000000 0x2 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 59>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <1>;
		clocks = <&gateclk 6>;
		status = "disabled";
	};

	pcie@3,0 {
		device_type = "pci";
		assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
		reg = <0x1800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
			  0x81000000 0 0 0x81000000 0x3 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 60>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <2>;
		clocks = <&gateclk 7>;
		status = "disabled";
	};

	pcie@4,0 {
		device_type = "pci";
		assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
		reg = <0x2000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
			  0x81000000 0 0 0x81000000 0x4 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 61>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <3>;
		clocks = <&gateclk 8>;
		status = "disabled";
	};

	pcie@5,0 {
		device_type = "pci";
		assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
		reg = <0x2800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
			  0x81000000 0 0 0x81000000 0x5 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 62>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 9>;
		status = "disabled";
	};

	pcie@6,0 {
		device_type = "pci";
		assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
		reg = <0x3000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
			  0x81000000 0 0 0x81000000 0x6 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 63>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <1>;
		clocks = <&gateclk 10>;
		status = "disabled";
	};

	pcie@7,0 {
		device_type = "pci";
		assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
		reg = <0x3800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
			  0x81000000 0 0 0x81000000 0x7 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 64>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <2>;
		clocks = <&gateclk 11>;
		status = "disabled";
	};

	pcie@8,0 {
		device_type = "pci";
		assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
		reg = <0x4000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
			  0x81000000 0 0 0x81000000 0x8 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 65>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <3>;
		clocks = <&gateclk 12>;
		status = "disabled";
	};

	pcie@9,0 {
		device_type = "pci";
		assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
		reg = <0x4800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
			  0x81000000 0 0 0x81000000 0x9 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 99>;
		marvell,pcie-port = <2>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 26>;
		status = "disabled";
	};

	pcie@10,0 {
		device_type = "pci";
		assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
		reg = <0x5000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
			  0x81000000 0 0 0x81000000 0xa 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 103>;
		marvell,pcie-port = <3>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 27>;
		status = "disabled";
	};
};
Commit	Line	Data
45361a4f TP	1	* Marvell EBU PCIe interfaces
	2
	3	Mandatory properties:
84384a45	4
45361a4f TP	5	- compatible: one of the following values:
	6	marvell,armada-370-pcie
	7	marvell,armada-xp-pcie
005625fc	8	marvell,kirkwood-pcie
45361a4f TP	9	- #address-cells, set to <3>
	10	- #size-cells, set to <2>
	11	- #interrupt-cells, set to <1>
	12	- bus-range: PCI bus numbers covered
	13	- device_type, set to "pci"
84384a45 TP	14	- ranges: ranges describing the MMIO registers to control the PCIe
	15	interfaces, and ranges describing the MBus windows needed to access
	16	the memory and I/O regions of each PCIe interface.
5b4deb65 TP	17	- msi-parent: Link to the hardware entity that serves as the Message
5b4deb65 TP	18	Signaled Interrupt controller for this PCI controller.
84384a45 TP	19
	20	The ranges describing the MMIO registers have the following layout:
	21
	22	0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
	23
	24	where:
	25
	26	* r is a 32-bits value that gives the offset of the MMIO
	27	registers of this PCIe interface, from the base of the internal
	28	registers.
	29
	30	* s is a 32-bits value that give the size of this MMIO
	31	registers area. This range entry translates the '0x82000000 0 r' PCI
	32	address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
	33	of the internal register window (as identified by MBUS_ID(0xf0,
	34	0x01)).
	35
	36	The ranges describing the MBus windows have the following layout:
	37
	38	0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
	39
	40	where:
	41
	42	* t is the type of the MBus window (as defined by the standard PCI DT
	43	bindings), 1 for I/O and 2 for memory.
45361a4f	44
84384a45 TP	45	* s is the PCI slot that corresponds to this PCIe interface
	46
	47	* w is the 'target ID' value for the MBus window
	48
	49	* a the 'attribute' value for the MBus window.
	50
	51	Since the location and size of the different MBus windows is not fixed in
	52	hardware, and only determined in runtime, those ranges cover the full first
	53	4 GB of the physical address space, and do not translate into a valid CPU
	54	address.
	55
	56	In addition, the device tree node must have sub-nodes describing each
45361a4f	57	PCIe interface, having the following mandatory properties:
84384a45	58
45361a4f TP	59	- reg: used only for interrupt mapping, so only the first four bytes
	60	are used to refer to the correct bus number and device number.
	61	- assigned-addresses: reference to the MMIO registers used to control
	62	this PCIe interface.
	63	- clocks: the clock associated to this PCIe interface
	64	- marvell,pcie-port: the physical PCIe port number
	65	- status: either "disabled" or "okay"
	66	- device_type, set to "pci"
	67	- #address-cells, set to <3>
	68	- #size-cells, set to <2>
	69	- #interrupt-cells, set to <1>
84384a45 TP	70	- ranges, translating the MBus windows ranges of the parent node into
84384a45 TP	71	standard PCI addresses.
45361a4f TP	72	- interrupt-map-mask and interrupt-map, standard PCI properties to
	73	define the mapping of the PCIe interface to interrupt numbers.
	74
	75	and the following optional properties:
	76	- marvell,pcie-lane: the physical PCIe lane number, for ports having
	77	multiple lanes. If this property is not found, we assume that the
	78	value is 0.
52ba992e SH	79	- reset-gpios: optional gpio to PERST#
52ba992e SH	80	- reset-delay-us: delay in us to wait after reset de-assertion
45361a4f TP	81
	82	Example:
	83
	84	pcie-controller {
	85	compatible = "marvell,armada-xp-pcie";
	86	status = "disabled";
	87	device_type = "pci";
	88
	89	#address-cells = <3>;
	90	#size-cells = <2>;
	91
	92	bus-range = <0x00 0xff>;
5b4deb65	93	msi-parent = <&mpic>;
45361a4f	94
84384a45 TP	95	ranges =
	96	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	97	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	98	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	99	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	100	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	101	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
	102	0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
	103	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	104	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	105	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
	106	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	107	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	108	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	109	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	110	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	111	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	112	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	113	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
	114
	115	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	116	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	117	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	118	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	119	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	120	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	121	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	122	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
	123
	124	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	125	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
	126
	127	0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
	128	0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
45361a4f TP	129
	130	pcie@1,0 {
	131	device_type = "pci";
84384a45	132	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
45361a4f TP	133	reg = <0x0800 0 0 0 0>;
	134	#address-cells = <3>;
	135	#size-cells = <2>;
	136	#interrupt-cells = <1>;
84384a45 TP	137	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
84384a45 TP	138	0x81000000 0 0 0x81000000 0x1 0 1 0>;
45361a4f TP	139	interrupt-map-mask = <0 0 0 0>;
	140	interrupt-map = <0 0 0 0 &mpic 58>;
	141	marvell,pcie-port = <0>;
	142	marvell,pcie-lane = <0>;
52ba992e SH	143	/* low-active PERST# reset on GPIO 25 */
	144	reset-gpios = <&gpio0 25 1>;
	145	/* wait 20ms for device settle after reset deassertion */
	146	reset-delay-us = <20000>;
45361a4f TP	147	clocks = <&gateclk 5>;
	148	status = "disabled";
	149	};
	150
	151	pcie@2,0 {
	152	device_type = "pci";
84384a45	153	assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
45361a4f TP	154	reg = <0x1000 0 0 0 0>;
	155	#address-cells = <3>;
	156	#size-cells = <2>;
	157	#interrupt-cells = <1>;
84384a45 TP	158	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
84384a45 TP	159	0x81000000 0 0 0x81000000 0x2 0 1 0>;
45361a4f TP	160	interrupt-map-mask = <0 0 0 0>;
	161	interrupt-map = <0 0 0 0 &mpic 59>;
	162	marvell,pcie-port = <0>;
	163	marvell,pcie-lane = <1>;
	164	clocks = <&gateclk 6>;
	165	status = "disabled";
	166	};
	167
	168	pcie@3,0 {
	169	device_type = "pci";
84384a45	170	assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
45361a4f TP	171	reg = <0x1800 0 0 0 0>;
	172	#address-cells = <3>;
	173	#size-cells = <2>;
	174	#interrupt-cells = <1>;
84384a45 TP	175	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
84384a45 TP	176	0x81000000 0 0 0x81000000 0x3 0 1 0>;
45361a4f TP	177	interrupt-map-mask = <0 0 0 0>;
	178	interrupt-map = <0 0 0 0 &mpic 60>;
	179	marvell,pcie-port = <0>;
	180	marvell,pcie-lane = <2>;
	181	clocks = <&gateclk 7>;
	182	status = "disabled";
	183	};
	184
	185	pcie@4,0 {
	186	device_type = "pci";
84384a45	187	assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
45361a4f TP	188	reg = <0x2000 0 0 0 0>;
	189	#address-cells = <3>;
	190	#size-cells = <2>;
	191	#interrupt-cells = <1>;
84384a45 TP	192	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
84384a45 TP	193	0x81000000 0 0 0x81000000 0x4 0 1 0>;
45361a4f TP	194	interrupt-map-mask = <0 0 0 0>;
	195	interrupt-map = <0 0 0 0 &mpic 61>;
	196	marvell,pcie-port = <0>;
	197	marvell,pcie-lane = <3>;
	198	clocks = <&gateclk 8>;
	199	status = "disabled";
	200	};
	201
	202	pcie@5,0 {
	203	device_type = "pci";
84384a45	204	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
45361a4f TP	205	reg = <0x2800 0 0 0 0>;
	206	#address-cells = <3>;
	207	#size-cells = <2>;
	208	#interrupt-cells = <1>;
84384a45 TP	209	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
84384a45 TP	210	0x81000000 0 0 0x81000000 0x5 0 1 0>;
45361a4f TP	211	interrupt-map-mask = <0 0 0 0>;
	212	interrupt-map = <0 0 0 0 &mpic 62>;
	213	marvell,pcie-port = <1>;
	214	marvell,pcie-lane = <0>;
	215	clocks = <&gateclk 9>;
	216	status = "disabled";
	217	};
	218
	219	pcie@6,0 {
	220	device_type = "pci";
84384a45	221	assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
45361a4f TP	222	reg = <0x3000 0 0 0 0>;
	223	#address-cells = <3>;
	224	#size-cells = <2>;
	225	#interrupt-cells = <1>;
84384a45 TP	226	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
84384a45 TP	227	0x81000000 0 0 0x81000000 0x6 0 1 0>;
45361a4f TP	228	interrupt-map-mask = <0 0 0 0>;
	229	interrupt-map = <0 0 0 0 &mpic 63>;
	230	marvell,pcie-port = <1>;
	231	marvell,pcie-lane = <1>;
	232	clocks = <&gateclk 10>;
	233	status = "disabled";
	234	};
	235
	236	pcie@7,0 {
	237	device_type = "pci";
84384a45	238	assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
45361a4f TP	239	reg = <0x3800 0 0 0 0>;
	240	#address-cells = <3>;
	241	#size-cells = <2>;
	242	#interrupt-cells = <1>;
84384a45 TP	243	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
84384a45 TP	244	0x81000000 0 0 0x81000000 0x7 0 1 0>;
45361a4f TP	245	interrupt-map-mask = <0 0 0 0>;
	246	interrupt-map = <0 0 0 0 &mpic 64>;
	247	marvell,pcie-port = <1>;
	248	marvell,pcie-lane = <2>;
	249	clocks = <&gateclk 11>;
	250	status = "disabled";
	251	};
	252
	253	pcie@8,0 {
	254	device_type = "pci";
84384a45	255	assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
45361a4f TP	256	reg = <0x4000 0 0 0 0>;
	257	#address-cells = <3>;
	258	#size-cells = <2>;
	259	#interrupt-cells = <1>;
84384a45 TP	260	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
84384a45 TP	261	0x81000000 0 0 0x81000000 0x8 0 1 0>;
45361a4f TP	262	interrupt-map-mask = <0 0 0 0>;
	263	interrupt-map = <0 0 0 0 &mpic 65>;
	264	marvell,pcie-port = <1>;
	265	marvell,pcie-lane = <3>;
	266	clocks = <&gateclk 12>;
	267	status = "disabled";
	268	};
84384a45	269
45361a4f TP	270	pcie@9,0 {
45361a4f TP	271	device_type = "pci";
84384a45	272	assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
45361a4f TP	273	reg = <0x4800 0 0 0 0>;
	274	#address-cells = <3>;
	275	#size-cells = <2>;
	276	#interrupt-cells = <1>;
84384a45 TP	277	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
84384a45 TP	278	0x81000000 0 0 0x81000000 0x9 0 1 0>;
45361a4f TP	279	interrupt-map-mask = <0 0 0 0>;
	280	interrupt-map = <0 0 0 0 &mpic 99>;
	281	marvell,pcie-port = <2>;
	282	marvell,pcie-lane = <0>;
	283	clocks = <&gateclk 26>;
	284	status = "disabled";
	285	};
	286
	287	pcie@10,0 {
	288	device_type = "pci";
84384a45	289	assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
45361a4f TP	290	reg = <0x5000 0 0 0 0>;
	291	#address-cells = <3>;
	292	#size-cells = <2>;
	293	#interrupt-cells = <1>;
84384a45 TP	294	ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
84384a45 TP	295	0x81000000 0 0 0x81000000 0xa 0 1 0>;
45361a4f TP	296	interrupt-map-mask = <0 0 0 0>;
	297	interrupt-map = <0 0 0 0 &mpic 103>;
	298	marvell,pcie-port = <3>;
	299	marvell,pcie-lane = <0>;
	300	clocks = <&gateclk 27>;
	301	status = "disabled";
	302	};
	303	};