[deliverable/linux.git] / Documentation / devicetree / bindings / pci / mvebu-pci.txt

* Marvell EBU PCIe interfaces

Mandatory properties:

- compatible: one of the following values:
    marvell,armada-370-pcie
    marvell,armada-xp-pcie
    marvell,kirkwood-pcie
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- bus-range: PCI bus numbers covered
- device_type, set to "pci"
- ranges: ranges describing the MMIO registers to control the PCIe
  interfaces, and ranges describing the MBus windows needed to access
  the memory and I/O regions of each PCIe interface.
- msi-parent: Link to the hardware entity that serves as the Message
  Signaled Interrupt controller for this PCI controller.

The ranges describing the MMIO registers have the following layout:

    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s

where:

  * r is a 32-bits value that gives the offset of the MMIO
  registers of this PCIe interface, from the base of the internal
  registers.

  * s is a 32-bits value that give the size of this MMIO
  registers area. This range entry translates the '0x82000000 0 r' PCI
  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  of the internal register window (as identified by MBUS_ID(0xf0,
  0x01)).

The ranges describing the MBus windows have the following layout:

    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0

where:

   * t is the type of the MBus window (as defined by the standard PCI DT
   bindings), 1 for I/O and 2 for memory.

   * s is the PCI slot that corresponds to this PCIe interface

   * w is the 'target ID' value for the MBus window

   * a the 'attribute' value for the MBus window.

Since the location and size of the different MBus windows is not fixed in
hardware, and only determined in runtime, those ranges cover the full first
4 GB of the physical address space, and do not translate into a valid CPU
address.

In addition, the device tree node must have sub-nodes describing each
PCIe interface, having the following mandatory properties:

- reg: used only for interrupt mapping, so only the first four bytes
  are used to refer to the correct bus number and device number.
- assigned-addresses: reference to the MMIO registers used to control
  this PCIe interface.
- clocks: the clock associated to this PCIe interface
- marvell,pcie-port: the physical PCIe port number
- status: either "disabled" or "okay"
- device_type, set to "pci"
- #address-cells, set to <3>
- #size-cells, set to <2>
- #interrupt-cells, set to <1>
- ranges, translating the MBus windows ranges of the parent node into
  standard PCI addresses.
- interrupt-map-mask and interrupt-map, standard PCI properties to
  define the mapping of the PCIe interface to interrupt numbers.

and the following optional properties:
- marvell,pcie-lane: the physical PCIe lane number, for ports having
  multiple lanes. If this property is not found, we assume that the
  value is 0.

Example:

pcie-controller {
	compatible = "marvell,armada-xp-pcie";
	status = "disabled";
	device_type = "pci";

	#address-cells = <3>;
	#size-cells = <2>;

	bus-range = <0x00 0xff>;
	msi-parent = <&mpic>;

	ranges =
	       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000	/* Port 0.0 registers */
		0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000	/* Port 2.0 registers */
		0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000	/* Port 0.1 registers */
		0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000	/* Port 0.2 registers */
		0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000	/* Port 0.3 registers */
		0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000	/* Port 1.0 registers */
		0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000	/* Port 3.0 registers */
		0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000	/* Port 1.1 registers */
		0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000	/* Port 1.2 registers */
		0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000	/* Port 1.3 registers */
		0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
		0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
		0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
		0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
		0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
		0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
		0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
		0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */

		0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
		0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
		0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
		0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
		0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
		0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
		0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
		0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */

		0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
		0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */

		0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
		0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;

	pcie@1,0 {
		device_type = "pci";
		assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
		reg = <0x0800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
			  0x81000000 0 0 0x81000000 0x1 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 58>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 5>;
		status = "disabled";
	};

	pcie@2,0 {
		device_type = "pci";
		assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
		reg = <0x1000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
			  0x81000000 0 0 0x81000000 0x2 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 59>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <1>;
		clocks = <&gateclk 6>;
		status = "disabled";
	};

	pcie@3,0 {
		device_type = "pci";
		assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
		reg = <0x1800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
			  0x81000000 0 0 0x81000000 0x3 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 60>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <2>;
		clocks = <&gateclk 7>;
		status = "disabled";
	};

	pcie@4,0 {
		device_type = "pci";
		assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
		reg = <0x2000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
			  0x81000000 0 0 0x81000000 0x4 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 61>;
		marvell,pcie-port = <0>;
		marvell,pcie-lane = <3>;
		clocks = <&gateclk 8>;
		status = "disabled";
	};

	pcie@5,0 {
		device_type = "pci";
		assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
		reg = <0x2800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
			  0x81000000 0 0 0x81000000 0x5 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 62>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 9>;
		status = "disabled";
	};

	pcie@6,0 {
		device_type = "pci";
		assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
		reg = <0x3000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
			  0x81000000 0 0 0x81000000 0x6 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 63>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <1>;
		clocks = <&gateclk 10>;
		status = "disabled";
	};

	pcie@7,0 {
		device_type = "pci";
		assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
		reg = <0x3800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
			  0x81000000 0 0 0x81000000 0x7 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 64>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <2>;
		clocks = <&gateclk 11>;
		status = "disabled";
	};

	pcie@8,0 {
		device_type = "pci";
		assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
		reg = <0x4000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
			  0x81000000 0 0 0x81000000 0x8 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 65>;
		marvell,pcie-port = <1>;
		marvell,pcie-lane = <3>;
		clocks = <&gateclk 12>;
		status = "disabled";
	};

	pcie@9,0 {
		device_type = "pci";
		assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
		reg = <0x4800 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
			  0x81000000 0 0 0x81000000 0x9 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 99>;
		marvell,pcie-port = <2>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 26>;
		status = "disabled";
	};

	pcie@10,0 {
		device_type = "pci";
		assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
		reg = <0x5000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
			  0x81000000 0 0 0x81000000 0xa 0 1 0>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &mpic 103>;
		marvell,pcie-port = <3>;
		marvell,pcie-lane = <0>;
		clocks = <&gateclk 27>;
		status = "disabled";
	};
};
Commit	Line	Data
45361a4f TP	1	* Marvell EBU PCIe interfaces
	2
	3	Mandatory properties:
84384a45	4
45361a4f TP	5	- compatible: one of the following values:
	6	marvell,armada-370-pcie
	7	marvell,armada-xp-pcie
005625fc	8	marvell,kirkwood-pcie
45361a4f TP	9	- #address-cells, set to <3>
	10	- #size-cells, set to <2>
	11	- #interrupt-cells, set to <1>
	12	- bus-range: PCI bus numbers covered
	13	- device_type, set to "pci"
84384a45 TP	14	- ranges: ranges describing the MMIO registers to control the PCIe
	15	interfaces, and ranges describing the MBus windows needed to access
	16	the memory and I/O regions of each PCIe interface.
5b4deb65 TP	17	- msi-parent: Link to the hardware entity that serves as the Message
5b4deb65 TP	18	Signaled Interrupt controller for this PCI controller.
84384a45 TP	19
	20	The ranges describing the MMIO registers have the following layout:
	21
	22	0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
	23
	24	where:
	25
	26	* r is a 32-bits value that gives the offset of the MMIO
	27	registers of this PCIe interface, from the base of the internal
	28	registers.
	29
	30	* s is a 32-bits value that give the size of this MMIO
	31	registers area. This range entry translates the '0x82000000 0 r' PCI
	32	address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
	33	of the internal register window (as identified by MBUS_ID(0xf0,
	34	0x01)).
	35
	36	The ranges describing the MBus windows have the following layout:
	37
	38	0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
	39
	40	where:
	41
	42	* t is the type of the MBus window (as defined by the standard PCI DT
	43	bindings), 1 for I/O and 2 for memory.
45361a4f	44
84384a45 TP	45	* s is the PCI slot that corresponds to this PCIe interface
	46
	47	* w is the 'target ID' value for the MBus window
	48
	49	* a the 'attribute' value for the MBus window.
	50
	51	Since the location and size of the different MBus windows is not fixed in
	52	hardware, and only determined in runtime, those ranges cover the full first
	53	4 GB of the physical address space, and do not translate into a valid CPU
	54	address.
	55
	56	In addition, the device tree node must have sub-nodes describing each
45361a4f	57	PCIe interface, having the following mandatory properties:
84384a45	58
45361a4f TP	59	- reg: used only for interrupt mapping, so only the first four bytes
	60	are used to refer to the correct bus number and device number.
	61	- assigned-addresses: reference to the MMIO registers used to control
	62	this PCIe interface.
	63	- clocks: the clock associated to this PCIe interface
	64	- marvell,pcie-port: the physical PCIe port number
	65	- status: either "disabled" or "okay"
	66	- device_type, set to "pci"
	67	- #address-cells, set to <3>
	68	- #size-cells, set to <2>
	69	- #interrupt-cells, set to <1>
84384a45 TP	70	- ranges, translating the MBus windows ranges of the parent node into
84384a45 TP	71	standard PCI addresses.
45361a4f TP	72	- interrupt-map-mask and interrupt-map, standard PCI properties to
	73	define the mapping of the PCIe interface to interrupt numbers.
	74
	75	and the following optional properties:
	76	- marvell,pcie-lane: the physical PCIe lane number, for ports having
	77	multiple lanes. If this property is not found, we assume that the
	78	value is 0.
	79
	80	Example:
	81
	82	pcie-controller {
	83	compatible = "marvell,armada-xp-pcie";
	84	status = "disabled";
	85	device_type = "pci";
	86
	87	#address-cells = <3>;
	88	#size-cells = <2>;
	89
	90	bus-range = <0x00 0xff>;
5b4deb65	91	msi-parent = <&mpic>;
45361a4f	92
84384a45 TP	93	ranges =
	94	<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
	95	0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
	96	0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
	97	0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
	98	0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
	99	0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
	100	0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
	101	0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
	102	0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
	103	0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
	104	0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
	105	0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
	106	0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
	107	0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
	108	0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
	109	0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
	110	0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
	111	0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
	112
	113	0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
	114	0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
	115	0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
	116	0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
	117	0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
	118	0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
	119	0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
	120	0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
	121
	122	0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
	123	0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
	124
	125	0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
	126	0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
45361a4f TP	127
	128	pcie@1,0 {
	129	device_type = "pci";
84384a45	130	assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
45361a4f TP	131	reg = <0x0800 0 0 0 0>;
	132	#address-cells = <3>;
	133	#size-cells = <2>;
	134	#interrupt-cells = <1>;
84384a45 TP	135	ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
84384a45 TP	136	0x81000000 0 0 0x81000000 0x1 0 1 0>;
45361a4f TP	137	interrupt-map-mask = <0 0 0 0>;
	138	interrupt-map = <0 0 0 0 &mpic 58>;
	139	marvell,pcie-port = <0>;
	140	marvell,pcie-lane = <0>;
	141	clocks = <&gateclk 5>;
	142	status = "disabled";
	143	};
	144
	145	pcie@2,0 {
	146	device_type = "pci";
84384a45	147	assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
45361a4f TP	148	reg = <0x1000 0 0 0 0>;
	149	#address-cells = <3>;
	150	#size-cells = <2>;
	151	#interrupt-cells = <1>;
84384a45 TP	152	ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
84384a45 TP	153	0x81000000 0 0 0x81000000 0x2 0 1 0>;
45361a4f TP	154	interrupt-map-mask = <0 0 0 0>;
	155	interrupt-map = <0 0 0 0 &mpic 59>;
	156	marvell,pcie-port = <0>;
	157	marvell,pcie-lane = <1>;
	158	clocks = <&gateclk 6>;
	159	status = "disabled";
	160	};
	161
	162	pcie@3,0 {
	163	device_type = "pci";
84384a45	164	assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
45361a4f TP	165	reg = <0x1800 0 0 0 0>;
	166	#address-cells = <3>;
	167	#size-cells = <2>;
	168	#interrupt-cells = <1>;
84384a45 TP	169	ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
84384a45 TP	170	0x81000000 0 0 0x81000000 0x3 0 1 0>;
45361a4f TP	171	interrupt-map-mask = <0 0 0 0>;
	172	interrupt-map = <0 0 0 0 &mpic 60>;
	173	marvell,pcie-port = <0>;
	174	marvell,pcie-lane = <2>;
	175	clocks = <&gateclk 7>;
	176	status = "disabled";
	177	};
	178
	179	pcie@4,0 {
	180	device_type = "pci";
84384a45	181	assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
45361a4f TP	182	reg = <0x2000 0 0 0 0>;
	183	#address-cells = <3>;
	184	#size-cells = <2>;
	185	#interrupt-cells = <1>;
84384a45 TP	186	ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
84384a45 TP	187	0x81000000 0 0 0x81000000 0x4 0 1 0>;
45361a4f TP	188	interrupt-map-mask = <0 0 0 0>;
	189	interrupt-map = <0 0 0 0 &mpic 61>;
	190	marvell,pcie-port = <0>;
	191	marvell,pcie-lane = <3>;
	192	clocks = <&gateclk 8>;
	193	status = "disabled";
	194	};
	195
	196	pcie@5,0 {
	197	device_type = "pci";
84384a45	198	assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
45361a4f TP	199	reg = <0x2800 0 0 0 0>;
	200	#address-cells = <3>;
	201	#size-cells = <2>;
	202	#interrupt-cells = <1>;
84384a45 TP	203	ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
84384a45 TP	204	0x81000000 0 0 0x81000000 0x5 0 1 0>;
45361a4f TP	205	interrupt-map-mask = <0 0 0 0>;
	206	interrupt-map = <0 0 0 0 &mpic 62>;
	207	marvell,pcie-port = <1>;
	208	marvell,pcie-lane = <0>;
	209	clocks = <&gateclk 9>;
	210	status = "disabled";
	211	};
	212
	213	pcie@6,0 {
	214	device_type = "pci";
84384a45	215	assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
45361a4f TP	216	reg = <0x3000 0 0 0 0>;
	217	#address-cells = <3>;
	218	#size-cells = <2>;
	219	#interrupt-cells = <1>;
84384a45 TP	220	ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
84384a45 TP	221	0x81000000 0 0 0x81000000 0x6 0 1 0>;
45361a4f TP	222	interrupt-map-mask = <0 0 0 0>;
	223	interrupt-map = <0 0 0 0 &mpic 63>;
	224	marvell,pcie-port = <1>;
	225	marvell,pcie-lane = <1>;
	226	clocks = <&gateclk 10>;
	227	status = "disabled";
	228	};
	229
	230	pcie@7,0 {
	231	device_type = "pci";
84384a45	232	assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
45361a4f TP	233	reg = <0x3800 0 0 0 0>;
	234	#address-cells = <3>;
	235	#size-cells = <2>;
	236	#interrupt-cells = <1>;
84384a45 TP	237	ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
84384a45 TP	238	0x81000000 0 0 0x81000000 0x7 0 1 0>;
45361a4f TP	239	interrupt-map-mask = <0 0 0 0>;
	240	interrupt-map = <0 0 0 0 &mpic 64>;
	241	marvell,pcie-port = <1>;
	242	marvell,pcie-lane = <2>;
	243	clocks = <&gateclk 11>;
	244	status = "disabled";
	245	};
	246
	247	pcie@8,0 {
	248	device_type = "pci";
84384a45	249	assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
45361a4f TP	250	reg = <0x4000 0 0 0 0>;
	251	#address-cells = <3>;
	252	#size-cells = <2>;
	253	#interrupt-cells = <1>;
84384a45 TP	254	ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
84384a45 TP	255	0x81000000 0 0 0x81000000 0x8 0 1 0>;
45361a4f TP	256	interrupt-map-mask = <0 0 0 0>;
	257	interrupt-map = <0 0 0 0 &mpic 65>;
	258	marvell,pcie-port = <1>;
	259	marvell,pcie-lane = <3>;
	260	clocks = <&gateclk 12>;
	261	status = "disabled";
	262	};
84384a45	263
45361a4f TP	264	pcie@9,0 {
45361a4f TP	265	device_type = "pci";
84384a45	266	assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
45361a4f TP	267	reg = <0x4800 0 0 0 0>;
	268	#address-cells = <3>;
	269	#size-cells = <2>;
	270	#interrupt-cells = <1>;
84384a45 TP	271	ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
84384a45 TP	272	0x81000000 0 0 0x81000000 0x9 0 1 0>;
45361a4f TP	273	interrupt-map-mask = <0 0 0 0>;
	274	interrupt-map = <0 0 0 0 &mpic 99>;
	275	marvell,pcie-port = <2>;
	276	marvell,pcie-lane = <0>;
	277	clocks = <&gateclk 26>;
	278	status = "disabled";
	279	};
	280
	281	pcie@10,0 {
	282	device_type = "pci";
84384a45	283	assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
45361a4f TP	284	reg = <0x5000 0 0 0 0>;
	285	#address-cells = <3>;
	286	#size-cells = <2>;
	287	#interrupt-cells = <1>;
84384a45 TP	288	ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
84384a45 TP	289	0x81000000 0 0 0x81000000 0xa 0 1 0>;
45361a4f TP	290	interrupt-map-mask = <0 0 0 0>;
	291	interrupt-map = <0 0 0 0 &mpic 103>;
	292	marvell,pcie-port = <3>;
	293	marvell,pcie-lane = <0>;
	294	clocks = <&gateclk 27>;
	295	status = "disabled";
	296	};
	297	};