Commit | Line | Data |
---|---|---|
80014ad5 TP |
1 | * Marvell Armada 7K/8K PCIe interface |
2 | ||
3 | This PCIe host controller is based on the Synopsis Designware PCIe IP | |
4 | and thus inherits all the common properties defined in designware-pcie.txt. | |
5 | ||
6 | Required properties: | |
7 | - compatible: "marvell,armada8k-pcie" | |
8 | - reg: must contain two register regions | |
9 | - the control register region | |
10 | - the config space region | |
11 | - reg-names: | |
12 | - "ctrl" for the control register region | |
13 | - "config" for the config space region | |
14 | - interrupts: Interrupt specifier for the PCIe controler | |
15 | - clocks: reference to the PCIe controller clock | |
16 | ||
17 | Example: | |
18 | ||
19 | pcie@f2600000 { | |
20 | compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; | |
21 | reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>; | |
22 | reg-names = "ctrl", "config"; | |
23 | #address-cells = <3>; | |
24 | #size-cells = <2>; | |
25 | #interrupt-cells = <1>; | |
26 | device_type = "pci"; | |
27 | dma-coherent; | |
28 | ||
29 | bus-range = <0 0xff>; | |
30 | ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */ | |
31 | 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */ | |
32 | interrupt-map-mask = <0 0 0 0>; | |
33 | interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
34 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
35 | num-lanes = <1>; | |
36 | clocks = <&cpm_syscon0 1 13>; | |
37 | status = "disabled"; | |
38 | }; |