projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d47b62f4 BD |
1 | Renesas AHB to PCI bridge |
| 2 | ------------------------- | |
| 3 | ||
| 4 | This is the bridge used internally to connect the USB controllers to the | |
| 5 | AHB. There is one bridge instance per USB port connected to the internal | |
| 6 | OHCI and EHCI controllers. | |
| 7 | ||
| 8 | Required properties: | |
| 9 | - compatible: "renesas,pci-r8a7790" for the R8A7790 SoC; | |
| de24c18c | 10 | "renesas,pci-r8a7791" for the R8A7791 SoC; |
| a176cd30 | 11 | "renesas,pci-r8a7793" for the R8A7793 SoC; |
| 3517652f SH |
12 | "renesas,pci-r8a7794" for the R8A7794 SoC; |
| 13 | "renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device | |
| 14 | ||
| 15 | ||
| 16 | When compatible with the generic version, nodes must list the | |
| 17 | SoC-specific version corresponding to the platform first | |
| 18 | followed by the generic version. | |
| 19 | ||
| d47b62f4 BD |
20 | - reg: A list of physical regions to access the device: the first is |
| 21 | the operational registers for the OHCI/EHCI controllers and the | |
| 22 | second is for the bridge configuration and control registers. | |
| 23 | - interrupts: interrupt for the device. | |
| 24 | - clocks: The reference to the device clock. | |
| 25 | - bus-range: The PCI bus number range; as this is a single bus, the range | |
| 26 | should be specified as the same value twice. | |
| 27 | - #address-cells: must be 3. | |
| 28 | - #size-cells: must be 2. | |
| 29 | - #interrupt-cells: must be 1. | |
| 30 | - interrupt-map: standard property used to define the mapping of the PCI | |
| 31 | interrupts to the GIC interrupts. | |
| 32 | - interrupt-map-mask: standard property that helps to define the interrupt | |
| 33 | mapping. | |
| 34 | ||
| 8d598cab PE |
35 | Optional properties: |
| 36 | - dma-ranges: a single range for the inbound memory region. If not supplied, | |
| 37 | defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the | |
| 38 | allowed combinations of address and size. | |
| 39 | ||
| d47b62f4 BD |
40 | Example SoC configuration: |
| 41 | ||
| 42 | pci0: pci@ee090000 { | |
| 3517652f | 43 | compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; |
| d47b62f4 BD |
44 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; |
| 45 | reg = <0x0 0xee090000 0x0 0xc00>, | |
| 46 | <0x0 0xee080000 0x0 0x1100>; | |
| 47 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 48 | status = "disabled"; | |
| 49 | ||
| 50 | bus-range = <0 0>; | |
| 51 | #address-cells = <3>; | |
| 52 | #size-cells = <2>; | |
| 53 | #interrupt-cells = <1>; | |
| 8d598cab | 54 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; |
| d47b62f4 BD |
55 | interrupt-map-mask = <0xff00 0 0 0x7>; |
| 56 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
| 57 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
| 58 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 59 | ||
| 60 | pci@0,1 { | |
| 61 | reg = <0x800 0 0 0 0>; | |
| 62 | device_type = "pci"; | |
| 63 | phys = <&usbphy 0 0>; | |
| 64 | phy-names = "usb"; | |
| 65 | }; | |
| 66 | ||
| 67 | pci@0,2 { | |
| 68 | reg = <0x1000 0 0 0 0>; | |
| 69 | device_type = "pci"; | |
| 70 | phys = <&usbphy 0 0>; | |
| 71 | phy-names = "usb"; | |
| 72 | }; | |
| 73 | }; | |
| 74 | ||
| 75 | Example board setup: | |
| 76 | ||
| 77 | &pci0 { | |
| 78 | status = "okay"; | |
| 79 | pinctrl-0 = <&usb0_pins>; | |
| 80 | pinctrl-names = "default"; | |
| 81 | }; |