[deliverable/linux.git] / Documentation / devicetree / bindings / pci / qcom,pcie.txt

* Qualcomm PCI express root complex

- compatible:
	Usage: required
	Value type: <stringlist>
	Definition: Value should contain
			- "qcom,pcie-ipq8064" for ipq8064
			- "qcom,pcie-apq8064" for apq8064
			- "qcom,pcie-apq8084" for apq8084

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: Register ranges as listed in the reg-names property

- reg-names:
	Usage: required
	Value type: <stringlist>
	Definition: Must include the following entries
			- "parf"   Qualcomm specific registers
			- "dbi"	   Designware PCIe registers
			- "elbi"   External local bus interface registers
			- "config" PCIe configuration space

- device_type:
	Usage: required
	Value type: <string>
	Definition: Should be "pci". As specified in designware-pcie.txt

- #address-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 3. As specified in designware-pcie.txt

- #size-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 2. As specified in designware-pcie.txt

- ranges:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- interrupts:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: MSI interrupt

- interrupt-names:
	Usage: required
	Value type: <stringlist>
	Definition: Should contain "msi"

- #interrupt-cells:
	Usage: required
	Value type: <u32>
	Definition: Should be 1. As specified in designware-pcie.txt

- interrupt-map-mask:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- interrupt-map:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: As specified in designware-pcie.txt

- clocks:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: List of phandle and clock specifier pairs as listed
		    in clock-names property

- clock-names:
	Usage: required
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "iface"	Configuration AHB clock

- clock-names:
	Usage: required for ipq/apq8064
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "core"	Clocks the pcie hw block
			- "phy"		Clocks the pcie PHY block
- clock-names:
	Usage: required for apq8084
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "aux"		Auxiliary (AUX) clock
			- "bus_master"	Master AXI clock
			- "bus_slave"	Slave AXI clock
- resets:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: List of phandle and reset specifier pairs as listed
		    in reset-names property

- reset-names:
	Usage: required for ipq/apq8064
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "axi"  AXI reset
			- "ahb"  AHB reset
			- "por"  POR reset
			- "pci"  PCI reset
			- "phy"  PHY reset

- reset-names:
	Usage: required for apq8084
	Value type: <stringlist>
	Definition: Should contain the following entries
			- "core" Core reset

- power-domains:
	Usage: required for apq8084
	Value type: <prop-encoded-array>
	Definition: A phandle and power domain specifier pair to the
		    power domain which is responsible for collapsing
		    and restoring power to the peripheral

- vdda-supply:
	Usage: required
	Value type: <phandle>
	Definition: A phandle to the core analog power supply

- vdda_phy-supply:
	Usage: required for ipq/apq8064
	Value type: <phandle>
	Definition: A phandle to the analog power supply for PHY

- vdda_refclk-supply:
	Usage: required for ipq/apq8064
	Value type: <phandle>
	Definition: A phandle to the analog power supply for IC which generates
		    reference clock

- phys:
	Usage: required for apq8084
	Value type: <phandle>
	Definition: List of phandle(s) as listed in phy-names property

- phy-names:
	Usage: required for apq8084
	Value type: <stringlist>
	Definition: Should contain "pciephy"

- <name>-gpios:
	Usage: optional
	Value type: <prop-encoded-array>
	Definition: List of phandle and gpio specifier pairs. Should contain
			- "perst-gpios"	PCIe endpoint reset signal line
			- "wake-gpios"	PCIe endpoint wake signal line

* Example for ipq/apq8064
	pcie@1b500000 {
		compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
		reg = <0x1b500000 0x1000
		       0x1b502000 0x80
		       0x1b600000 0x100
		       0x0ff00000 0x100000>;
		reg-names = "dbi", "elbi", "parf", "config";
		device_type = "pci";
		linux,pci-domain = <0>;
		bus-range = <0x00 0xff>;
		num-lanes = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
		clocks = <&gcc PCIE_A_CLK>,
			 <&gcc PCIE_H_CLK>,
			 <&gcc PCIE_PHY_CLK>;
		clock-names = "core", "iface", "phy";
		resets = <&gcc PCIE_ACLK_RESET>,
			 <&gcc PCIE_HCLK_RESET>,
			 <&gcc PCIE_POR_RESET>,
			 <&gcc PCIE_PCI_RESET>,
			 <&gcc PCIE_PHY_RESET>;
		reset-names = "axi", "ahb", "por", "pci", "phy";
		pinctrl-0 = <&pcie_pins_default>;
		pinctrl-names = "default";
	};

* Example for apq8084
	pcie0@fc520000 {
		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
		reg = <0xfc520000 0x2000>,
		      <0xff000000 0x1000>,
		      <0xff001000 0x1000>,
		      <0xff002000 0x2000>;
		reg-names = "parf", "dbi", "elbi", "config";
		device_type = "pci";
		linux,pci-domain = <0>;
		bus-range = <0x00 0xff>;
		num-lanes = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
			  0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
		interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
				<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
				<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
				<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
		clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
			 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
			 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
			 <&gcc GCC_PCIE_0_AUX_CLK>;
		clock-names = "iface", "master_bus", "slave_bus", "aux";
		resets = <&gcc GCC_PCIE_0_BCR>;
		reset-names = "core";
		power-domains = <&gcc PCIE0_GDSC>;
		vdda-supply = <&pma8084_l3>;
		phys = <&pciephy0>;
		phy-names = "pciephy";
		perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
		pinctrl-0 = <&pcie0_pins_default>;
		pinctrl-names = "default";
	};
Commit	Line	Data
845d5ca2 SV	1	* Qualcomm PCI express root complex
	2
	3	- compatible:
	4	Usage: required
	5	Value type: <stringlist>
	6	Definition: Value should contain
	7	- "qcom,pcie-ipq8064" for ipq8064
	8	- "qcom,pcie-apq8064" for apq8064
	9	- "qcom,pcie-apq8084" for apq8084
	10
	11	- reg:
	12	Usage: required
	13	Value type: <prop-encoded-array>
	14	Definition: Register ranges as listed in the reg-names property
	15
	16	- reg-names:
	17	Usage: required
	18	Value type: <stringlist>
	19	Definition: Must include the following entries
	20	- "parf" Qualcomm specific registers
	21	- "dbi" Designware PCIe registers
	22	- "elbi" External local bus interface registers
	23	- "config" PCIe configuration space
	24
	25	- device_type:
	26	Usage: required
	27	Value type: <string>
	28	Definition: Should be "pci". As specified in designware-pcie.txt
	29
	30	- #address-cells:
	31	Usage: required
	32	Value type: <u32>
	33	Definition: Should be 3. As specified in designware-pcie.txt
	34
	35	- #size-cells:
	36	Usage: required
	37	Value type: <u32>
	38	Definition: Should be 2. As specified in designware-pcie.txt
	39
	40	- ranges:
	41	Usage: required
	42	Value type: <prop-encoded-array>
	43	Definition: As specified in designware-pcie.txt
	44
	45	- interrupts:
	46	Usage: required
	47	Value type: <prop-encoded-array>
	48	Definition: MSI interrupt
	49
	50	- interrupt-names:
	51	Usage: required
	52	Value type: <stringlist>
	53	Definition: Should contain "msi"
	54
	55	- #interrupt-cells:
	56	Usage: required
	57	Value type: <u32>
	58	Definition: Should be 1. As specified in designware-pcie.txt
	59
	60	- interrupt-map-mask:
	61	Usage: required
	62	Value type: <prop-encoded-array>
	63	Definition: As specified in designware-pcie.txt
	64
65	- interrupt-map:
66	Usage: required
67	Value type: <prop-encoded-array>
68	Definition: As specified in designware-pcie.txt
69
70	- clocks:
71	Usage: required
72	Value type: <prop-encoded-array>
73	Definition: List of phandle and clock specifier pairs as listed
74	in clock-names property
75
76	- clock-names:
77	Usage: required
78	Value type: <stringlist>
79	Definition: Should contain the following entries
80	- "iface" Configuration AHB clock
81
82	- clock-names:
83	Usage: required for ipq/apq8064
84	Value type: <stringlist>
85	Definition: Should contain the following entries
86	- "core" Clocks the pcie hw block
87	- "phy" Clocks the pcie PHY block
88	- clock-names:
89	Usage: required for apq8084
90	Value type: <stringlist>
91	Definition: Should contain the following entries
92	- "aux" Auxiliary (AUX) clock
93	- "bus_master" Master AXI clock
94	- "bus_slave" Slave AXI clock
95	- resets:
96	Usage: required
97	Value type: <prop-encoded-array>
98	Definition: List of phandle and reset specifier pairs as listed
99	in reset-names property
100
101	- reset-names:
102	Usage: required for ipq/apq8064
103	Value type: <stringlist>
104	Definition: Should contain the following entries
105	- "axi" AXI reset
106	- "ahb" AHB reset
107	- "por" POR reset
108	- "pci" PCI reset
109	- "phy" PHY reset
110
111	- reset-names:
112	Usage: required for apq8084
113	Value type: <stringlist>
114	Definition: Should contain the following entries
115	- "core" Core reset
116
117	- power-domains:
118	Usage: required for apq8084
119	Value type: <prop-encoded-array>
120	Definition: A phandle and power domain specifier pair to the
121	power domain which is responsible for collapsing
122	and restoring power to the peripheral
123
124	- vdda-supply:
125	Usage: required
126	Value type: <phandle>
127	Definition: A phandle to the core analog power supply
128
129	- vdda_phy-supply:
130	Usage: required for ipq/apq8064
131	Value type: <phandle>
132	Definition: A phandle to the analog power supply for PHY
133
134	- vdda_refclk-supply:
135	Usage: required for ipq/apq8064
136	Value type: <phandle>
137	Definition: A phandle to the analog power supply for IC which generates
138	reference clock
139
140	- phys:
141	Usage: required for apq8084
142	Value type: <phandle>
143	Definition: List of phandle(s) as listed in phy-names property
144
145	- phy-names:
146	Usage: required for apq8084
147	Value type: <stringlist>
148	Definition: Should contain "pciephy"
149
150	- <name>-gpios:
151	Usage: optional
152	Value type: <prop-encoded-array>
153	Definition: List of phandle and gpio specifier pairs. Should contain
154	- "perst-gpios" PCIe endpoint reset signal line
155	- "wake-gpios" PCIe endpoint wake signal line
156
157	* Example for ipq/apq8064
158	pcie@1b500000 {
159	compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
160	reg = <0x1b500000 0x1000
161	0x1b502000 0x80
162	0x1b600000 0x100
163	0x0ff00000 0x100000>;
164	reg-names = "dbi", "elbi", "parf", "config";
165	device_type = "pci";
166	linux,pci-domain = <0>;
167	bus-range = <0x00 0xff>;
168	num-lanes = <1>;
169	#address-cells = <3>;
170	#size-cells = <2>;
171	ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
172	0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
173	interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
174	interrupt-names = "msi";
175	#interrupt-cells = <1>;
176	interrupt-map-mask = <0 0 0 0x7>;
177	interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
178	<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
179	<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
180	<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
181	clocks = <&gcc PCIE_A_CLK>,
182	<&gcc PCIE_H_CLK>,
183	<&gcc PCIE_PHY_CLK>;
184	clock-names = "core", "iface", "phy";
185	resets = <&gcc PCIE_ACLK_RESET>,
186	<&gcc PCIE_HCLK_RESET>,
187	<&gcc PCIE_POR_RESET>,
188	<&gcc PCIE_PCI_RESET>,
189	<&gcc PCIE_PHY_RESET>;
190	reset-names = "axi", "ahb", "por", "pci", "phy";
191	pinctrl-0 = <&pcie_pins_default>;
192	pinctrl-names = "default";
193	};
194
195	* Example for apq8084
196	pcie0@fc520000 {
197	compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
198	reg = <0xfc520000 0x2000>,
199	<0xff000000 0x1000>,
200	<0xff001000 0x1000>,
201	<0xff002000 0x2000>;
202	reg-names = "parf", "dbi", "elbi", "config";
203	device_type = "pci";
204	linux,pci-domain = <0>;
205	bus-range = <0x00 0xff>;
206	num-lanes = <1>;
207	#address-cells = <3>;
208	#size-cells = <2>;
209	ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
210	0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
211	interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
212	interrupt-names = "msi";
213	#interrupt-cells = <1>;
214	interrupt-map-mask = <0 0 0 0x7>;
215	interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
216	<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
217	<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
218	<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
219	clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
220	<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
221	<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
222	<&gcc GCC_PCIE_0_AUX_CLK>;
223	clock-names = "iface", "master_bus", "slave_bus", "aux";
224	resets = <&gcc GCC_PCIE_0_BCR>;
225	reset-names = "core";
226	power-domains = <&gcc PCIE0_GDSC>;
227	vdda-supply = <&pma8084_l3>;
228	phys = <&pciephy0>;
229	phy-names = "pciephy";
230	perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
231	pinctrl-0 = <&pcie0_pins_default>;
232	pinctrl-names = "default";
233	};