Commit | Line | Data |
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1db823ee LS |
1 | * Samsung Exynos 5440 PCIe interface |
2 | ||
3 | This PCIe host controller is based on the Synopsis Designware PCIe IP | |
4 | and thus inherits all the common properties defined in designware-pcie.txt. | |
5 | ||
6 | Required properties: | |
7 | - compatible: "samsung,exynos5440-pcie" | |
8 | - reg: base addresses and lengths of the pcie controller, | |
9 | the phy controller, additional register for the phy controller. | |
10 | - interrupts: A list of interrupt outputs for level interrupt, | |
11 | pulse interrupt, special interrupt. | |
12 | ||
13 | Example: | |
14 | ||
15 | SoC specific DT Entry: | |
16 | ||
17 | pcie@290000 { | |
18 | compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; | |
19 | reg = <0x290000 0x1000 | |
20 | 0x270000 0x1000 | |
21 | 0x271000 0x40>; | |
22 | interrupts = <0 20 0>, <0 21 0>, <0 22 0>; | |
23 | clocks = <&clock 28>, <&clock 27>; | |
24 | clock-names = "pcie", "pcie_bus"; | |
25 | #address-cells = <3>; | |
26 | #size-cells = <2>; | |
27 | device_type = "pci"; | |
28 | ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ | |
29 | 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ | |
30 | 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ | |
31 | #interrupt-cells = <1>; | |
32 | interrupt-map-mask = <0 0 0 0>; | |
33 | interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
34 | num-lanes = <4>; | |
35 | }; | |
36 | ||
37 | pcie@2a0000 { | |
38 | compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; | |
39 | reg = <0x2a0000 0x1000 | |
40 | 0x272000 0x1000 | |
41 | 0x271040 0x40>; | |
42 | interrupts = <0 23 0>, <0 24 0>, <0 25 0>; | |
43 | clocks = <&clock 29>, <&clock 27>; | |
44 | clock-names = "pcie", "pcie_bus"; | |
45 | #address-cells = <3>; | |
46 | #size-cells = <2>; | |
47 | device_type = "pci"; | |
48 | ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ | |
49 | 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ | |
50 | 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ | |
51 | #interrupt-cells = <1>; | |
52 | interrupt-map-mask = <0 0 0 0>; | |
53 | interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
54 | num-lanes = <4>; | |
55 | }; | |
56 | ||
57 | Board specific DT Entry: | |
58 | ||
59 | pcie@290000 { | |
60 | reset-gpio = <&pin_ctrl 5 0>; | |
61 | }; | |
62 | ||
63 | pcie@2a0000 { | |
64 | reset-gpio = <&pin_ctrl 22 0>; | |
65 | }; |