projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ab597d35 BKG |
1 | * Xilinx NWL PCIe Root Port Bridge DT description |
| 2 | ||
| 3 | Required properties: | |
| 4 | - compatible: Should contain "xlnx,nwl-pcie-2.11" | |
| 5 | - #address-cells: Address representation for root ports, set to <3> | |
| 6 | - #size-cells: Size representation for root ports, set to <2> | |
| 7 | - #interrupt-cells: specifies the number of cells needed to encode an | |
| 8 | interrupt source. The value must be 1. | |
| 9 | - reg: Should contain Bridge, PCIe Controller registers location, | |
| 10 | configuration space, and length | |
| 11 | - reg-names: Must include the following entries: | |
| 12 | "breg": bridge registers | |
| 13 | "pcireg": PCIe controller registers | |
| 14 | "cfg": configuration space region | |
| 15 | - device_type: must be "pci" | |
| 16 | - interrupts: Should contain NWL PCIe interrupt | |
| 17 | - interrupt-names: Must include the following entries: | |
| 18 | "msi1, msi0": interrupt asserted when MSI is received | |
| 19 | "intx": interrupt asserted when a legacy interrupt is received | |
| 20 | "misc": interrupt asserted when miscellaneous is received | |
| 21 | - interrupt-map-mask and interrupt-map: standard PCI properties to define the | |
| 22 | mapping of the PCI interface to interrupt numbers. | |
| 23 | - ranges: ranges for the PCI memory regions (I/O space region is not | |
| 24 | supported by hardware) | |
| 25 | Please refer to the standard PCI bus binding document for a more | |
| 26 | detailed explanation | |
| 27 | - msi-controller: indicates that this is MSI controller node | |
| 28 | - msi-parent: MSI parent of the root complex itself | |
| 29 | - legacy-interrupt-controller: Interrupt controller device node for Legacy interrupts | |
| 30 | - interrupt-controller: identifies the node as an interrupt controller | |
| 31 | - #interrupt-cells: should be set to 1 | |
| 32 | - #address-cells: specifies the number of cells needed to encode an | |
| 33 | address. The value must be 0. | |
| 34 | ||
| 35 | ||
| 36 | Example: | |
| 37 | ++++++++ | |
| 38 | ||
| 39 | nwl_pcie: pcie@fd0e0000 { | |
| 40 | #address-cells = <3>; | |
| 41 | #size-cells = <2>; | |
| 42 | compatible = "xlnx,nwl-pcie-2.11"; | |
| 43 | #interrupt-cells = <1>; | |
| 44 | msi-controller; | |
| 45 | device_type = "pci"; | |
| 46 | interrupt-parent = <&gic>; | |
| 47 | interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; | |
| 48 | interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; | |
| 49 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 50 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
| 51 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
| 52 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
| 53 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
| 54 | ||
| 55 | msi-parent = <&nwl_pcie>; | |
| 56 | reg = <0x0 0xfd0e0000 0x0 0x1000>, | |
| 57 | <0x0 0xfd480000 0x0 0x1000>, | |
| 58 | <0x0 0xe0000000 0x0 0x1000000>; | |
| 59 | reg-names = "breg", "pcireg", "cfg"; | |
| 60 | ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; | |
| 61 | ||
| 62 | pcie_intc: legacy-interrupt-controller { | |
| 63 | interrupt-controller; | |
| 64 | #address-cells = <0>; | |
| 65 | #interrupt-cells = <1>; | |
| 66 | }; | |
| 67 | ||
| 68 | }; |