[deliverable/linux.git] / Documentation / devicetree / bindings / pci / xilinx-pcie.txt

* Xilinx AXI PCIe Root Port Bridge DT description

Required properties:
- #address-cells: Address representation for root ports, set to <3>
- #size-cells: Size representation for root ports, set to <2>
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.
- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
- reg: Should contain AXI PCIe registers location and length
- device_type: must be "pci"
- interrupts: Should contain AXI PCIe interrupt
- interrupt-map-mask,
  interrupt-map: standard PCI properties to define the mapping of the
	PCI interface to interrupt numbers.
- ranges: ranges for the PCI memory regions (I/O space region is not
	supported by hardware)
	Please refer to the standard PCI bus binding document for a more
	detailed explanation

Optional properties for Zynq/Microblaze:
- bus-range: PCI bus numbers covered

Interrupt controller child node
+++++++++++++++++++++++++++++++
Required properties:
- interrupt-controller: identifies the node as an interrupt controller
- #address-cells: specifies the number of cells needed to encode an
	address. The value must be 0.
- #interrupt-cells: specifies the number of cells needed to encode an
	interrupt source. The value must be 1.

NOTE:
The core provides a single interrupt for both INTx/MSI messages. So,
created a interrupt controller node to support 'interrupt-map' DT
functionality.  The driver will create an IRQ domain for this map, decode
the four INTx interrupts in ISR and route them to this domain.


Example:
++++++++
Zynq:
	pci_express: axi-pcie@50000000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		compatible = "xlnx,axi-pcie-host-1.00.a";
		reg = < 0x50000000 0x1000000 >;
		device_type = "pci";
		interrupts = < 0 52 4 >;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc 1>,
				<0 0 0 2 &pcie_intc 2>,
				<0 0 0 3 &pcie_intc 3>,
				<0 0 0 4 &pcie_intc 4>;
		ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;

		pcie_intc: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};


Microblaze:
	pci_express: axi-pcie@10000000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		compatible = "xlnx,axi-pcie-host-1.00.a";
		reg = <0x10000000 0x4000000>;
		device_type = "pci";
		interrupt-parent = <&microblaze_0_intc>;
		interrupts = <1 2>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc 1>,
				<0 0 0 2 &pcie_intc 2>,
				<0 0 0 3 &pcie_intc 3>,
				<0 0 0 4 &pcie_intc 4>;
		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;

		pcie_intc: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};

	};
Commit	Line	Data
8961def5 ST	1	* Xilinx AXI PCIe Root Port Bridge DT description
	2
	3	Required properties:
	4	- #address-cells: Address representation for root ports, set to <3>
	5	- #size-cells: Size representation for root ports, set to <2>
	6	- #interrupt-cells: specifies the number of cells needed to encode an
	7	interrupt source. The value must be 1.
	8	- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
	9	- reg: Should contain AXI PCIe registers location and length
	10	- device_type: must be "pci"
	11	- interrupts: Should contain AXI PCIe interrupt
	12	- interrupt-map-mask,
	13	interrupt-map: standard PCI properties to define the mapping of the
	14	PCI interface to interrupt numbers.
	15	- ranges: ranges for the PCI memory regions (I/O space region is not
	16	supported by hardware)
	17	Please refer to the standard PCI bus binding document for a more
	18	detailed explanation
	19
e5d4b200	20	Optional properties for Zynq/Microblaze:
8961def5 ST	21	- bus-range: PCI bus numbers covered
	22
	23	Interrupt controller child node
	24	+++++++++++++++++++++++++++++++
	25	Required properties:
	26	- interrupt-controller: identifies the node as an interrupt controller
	27	- #address-cells: specifies the number of cells needed to encode an
	28	address. The value must be 0.
	29	- #interrupt-cells: specifies the number of cells needed to encode an
	30	interrupt source. The value must be 1.
	31
	32	NOTE:
	33	The core provides a single interrupt for both INTx/MSI messages. So,
	34	created a interrupt controller node to support 'interrupt-map' DT
	35	functionality. The driver will create an IRQ domain for this map, decode
	36	the four INTx interrupts in ISR and route them to this domain.
	37
	38
	39	Example:
	40	++++++++
e5d4b200	41	Zynq:
8961def5 ST	42	pci_express: axi-pcie@50000000 {
	43	#address-cells = <3>;
	44	#size-cells = <2>;
	45	#interrupt-cells = <1>;
	46	compatible = "xlnx,axi-pcie-host-1.00.a";
e5d4b200	47	reg = < 0x50000000 0x1000000 >;
8961def5 ST	48	device_type = "pci";
	49	interrupts = < 0 52 4 >;
	50	interrupt-map-mask = <0 0 0 7>;
	51	interrupt-map = <0 0 0 1 &pcie_intc 1>,
	52	<0 0 0 2 &pcie_intc 2>,
	53	<0 0 0 3 &pcie_intc 3>,
	54	<0 0 0 4 &pcie_intc 4>;
	55	ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
	56
	57	pcie_intc: interrupt-controller {
	58	interrupt-controller;
	59	#address-cells = <0>;
	60	#interrupt-cells = <1>;
a6e86403	61	};
8961def5	62	};
e5d4b200 BKG	63
	64
	65	Microblaze:
	66	pci_express: axi-pcie@10000000 {
	67	#address-cells = <3>;
	68	#size-cells = <2>;
	69	#interrupt-cells = <1>;
	70	compatible = "xlnx,axi-pcie-host-1.00.a";
	71	reg = <0x10000000 0x4000000>;
	72	device_type = "pci";
	73	interrupt-parent = <&microblaze_0_intc>;
	74	interrupts = <1 2>;
	75	interrupt-map-mask = <0 0 0 7>;
	76	interrupt-map = <0 0 0 1 &pcie_intc 1>,
	77	<0 0 0 2 &pcie_intc 2>,
	78	<0 0 0 3 &pcie_intc 3>,
	79	<0 0 0 4 &pcie_intc 4>;
	80	ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
	81
	82	pcie_intc: interrupt-controller {
	83	interrupt-controller;
	84	#address-cells = <0>;
	85	#interrupt-cells = <1>;
	86	};
	87
	88	};