[deliverable/linux.git] / Documentation / devicetree / bindings / phy / phy-stih407-usb.txt

ST STiH407 USB PHY controller

This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.

Required properties:
- compatible		: should be "st,stih407-usb2-phy"
- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
- resets		: list of phandle and reset specifier pairs. There should be two entries, one
			  for the whole phy and one for the port
- reset-names		: list of reset signal names. Should be "global" and "port"
See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
See: Documentation/devicetree/bindings/reset/reset.txt

Example:

usb2_picophy0: usbpicophy@f8 {
	compatible	= "st,stih407-usb2-phy";
	#phy-cells	= <0>;
	st,syscfg	= <&syscfg_core 0x100 0xf4>;
	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,
			  <&picophyreset STIH407_PICOPHY0_RESET>;
	reset-names	= "global", "port";
};
Commit	Line	Data
ea1e53c7 PG	1	ST STiH407 USB PHY controller
	2
	3	This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
	4	host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.
	5
	6	Required properties:
	7	- compatible : should be "st,stih407-usb2-phy"
937127fe	8	- st,syscfg : phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
ea1e53c7 PG	9	- resets : list of phandle and reset specifier pairs. There should be two entries, one
	10	for the whole phy and one for the port
	11	- reset-names : list of reset signal names. Should be "global" and "port"
	12	See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
	13	See: Documentation/devicetree/bindings/reset/reset.txt
	14
	15	Example:
	16
	17	usb2_picophy0: usbpicophy@f8 {
	18	compatible = "st,stih407-usb2-phy";
ea1e53c7	19	#phy-cells = <0>;
937127fe	20	st,syscfg = <&syscfg_core 0x100 0xf4>;
ea1e53c7 PG	21	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	22	<&picophyreset STIH407_PICOPHY0_RESET>;
	23	reset-names = "global", "port";
	24	};