[deliverable/linux.git] / Documentation / devicetree / bindings / pinctrl / atmel,at91-pinctrl.txt

* Atmel AT91 Pinmux Controller

The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require
different PAD settings (like pull up, keeper, etc) the contoller controls
also the PAD settings parameters.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

Atmel AT91 pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and config
of the pins in that group. The 'pins' selects the function mode(also named pin
mode) this pin can work on and the 'config' configures various pad settings
such as pull-up, multi drive, etc.

Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
		or "atmel,sama5d3-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
  configured in this periph mode. All the periph and bank need to be describe.

How to create such array:

Each column will represent the possible peripheral of the pinctrl
Each line will represent a pio bank

Take an example on the 9260
Peripheral: 2 ( A and B)
Bank: 3 (A, B and C)
=>

  /*    A         B     */
  0xffffffff 0xffc00c3b  /* pioA */
  0xffffffff 0x7fff3ccf  /* pioB */
  0xffffffff 0x007fffff  /* pioC */

For each peripheral/bank we will descibe in a u32 if a pin can be
configured in it by putting 1 to the pin bit (1 << pin)

Let's take the pioA on peripheral B
From the datasheet Table 10-2.
Peripheral B
PA0	MCDB0
PA1	MCCDB
PA2
PA3	MCDB3
PA4	MCDB2
PA5	MCDB1
PA6
PA7
PA8
PA9
PA10	ETX2
PA11	ETX3
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22	ETXER
PA23	ETX2
PA24	ETX3
PA25	ERX2
PA26	ERX3
PA27	ERXCK
PA28	ECRS
PA29	ECOL
PA30	RXD4
PA31	TXD4

=> 0xffc00c3b

Required properties for pin configuration node:
- atmel,pins: 4 integers array, represents a group of pins mux and config
  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
  The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...

Bits used for CONFIG:
PULL_UP		(1 << 0): indicate this pin needs a pull up.
MULTIDRIVE	(1 << 1): indicate this pin needs to be configured as multi-drive.
			Multi-drive is equivalent to open-drain type output.
DEGLITCH	(1 << 2): indicate this pin needs deglitch.
PULL_DOWN	(1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT	(1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
			following values:
				00 - No change (reset state value kept)
				01 - Low
				10 - Medium
				11 - High
DEBOUNCE	(1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL	(0x3fff << 17): debounce value.

NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:
1. We have pin function node defined under at91 controller node to represent
   what pinmux functions this SoC supports.
2. The driver can use the function node's name and pin configuration node's
   name describe the pin function and group hierarchy.
   For example, Linux at91 pinctrl driver takes the function node's name
   as the function name and pin configuration node's name as group name to
   create the map table.
3. Each pin configuration node should have a phandle, devices can set pins
   configurations by referring to the phandle of that pin configuration node.
4. The gpio controller must be describe in the pinctrl simple-bus.

Examples:

pinctrl@fffff400 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
	reg = <0xfffff400 0x600>;

	atmel,mux-mask = <
	      /*    A         B     */
	       0xffffffff 0xffc00c3b  /* pioA */
	       0xffffffff 0x7fff3ccf  /* pioB */
	       0xffffffff 0x007fffff  /* pioC */
	      >;

	/* shared pinctrl settings */
	dbgu {
		pinctrl_dbgu: dbgu-0 {
			atmel,pins =
				<1 14 0x1 0x0	/* PB14 periph A */
				 1 15 0x1 0x1>;	/* PB15 periph A with pullup */
		};
	};
};

dbgu: serial@fffff200 {
	compatible = "atmel,at91sam9260-usart";
	reg = <0xfffff200 0x200>;
	interrupts = <1 4 7>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dbgu>;
	status = "disabled";
};
Commit	Line	Data
6732ae5c JCPV	1	* Atmel AT91 Pinmux Controller
6732ae5c JCPV	2
372c1d6d	3	The AT91 Pinmux Controller, enables the IC
6732ae5c JCPV	4	to share one PAD to several functional blocks. The sharing is done by
	5	multiplexing the PAD input/output signals. For each PAD there are up to
	6	8 muxing options (called periph modes). Since different modules require
	7	different PAD settings (like pull up, keeper, etc) the contoller controls
	8	also the PAD settings parameters.
	9
	10	Please refer to pinctrl-bindings.txt in this directory for details of the
	11	common pinctrl bindings used by client devices, including the meaning of the
	12	phrase "pin configuration node".
	13
	14	Atmel AT91 pin configuration node is a node of a group of pins which can be
	15	used for a specific device or function. This node represents both mux and config
	16	of the pins in that group. The 'pins' selects the function mode(also named pin
	17	mode) this pin can work on and the 'config' configures various pad settings
	18	such as pull-up, multi drive, etc.
	19
	20	Required properties for iomux controller:
2467f110	21	- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
2de5da57	22	or "atmel,sama5d3-pinctrl"
6732ae5c JCPV	23	- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
	24	configured in this periph mode. All the periph and bank need to be describe.
	25
	26	How to create such array:
	27
	28	Each column will represent the possible peripheral of the pinctrl
	29	Each line will represent a pio bank
	30
	31	Take an example on the 9260
	32	Peripheral: 2 ( A and B)
	33	Bank: 3 (A, B and C)
	34	=>
	35
	36	/* A B */
	37	0xffffffff 0xffc00c3b /* pioA */
	38	0xffffffff 0x7fff3ccf /* pioB */
	39	0xffffffff 0x007fffff /* pioC */
	40
c9f3f2d8	41	For each peripheral/bank we will descibe in a u32 if a pin can be
6732ae5c JCPV	42	configured in it by putting 1 to the pin bit (1 << pin)
	43
	44	Let's take the pioA on peripheral B
	45	From the datasheet Table 10-2.
	46	Peripheral B
	47	PA0 MCDB0
	48	PA1 MCCDB
	49	PA2
	50	PA3 MCDB3
	51	PA4 MCDB2
	52	PA5 MCDB1
	53	PA6
	54	PA7
	55	PA8
	56	PA9
	57	PA10 ETX2
	58	PA11 ETX3
	59	PA12
	60	PA13
	61	PA14
	62	PA15
	63	PA16
	64	PA17
	65	PA18
	66	PA19
	67	PA20
	68	PA21
	69	PA22 ETXER
	70	PA23 ETX2
	71	PA24 ETX3
	72	PA25 ERX2
	73	PA26 ERX3
	74	PA27 ERXCK
	75	PA28 ECRS
	76	PA29 ECOL
	77	PA30 RXD4
	78	PA31 TXD4
	79
	80	=> 0xffc00c3b
	81
	82	Required properties for pin configuration node:
	83	- atmel,pins: 4 integers array, represents a group of pins mux and config
	84	setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
45976c01 RG	85	The PERIPH 0 means gpio, PERIPH 1 is periph A, PERIPH 2 is periph B...
45976c01 RG	86	PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
6732ae5c JCPV	87
6732ae5c JCPV	88	Bits used for CONFIG:
2de5da57 MR	89	PULL_UP (1 << 0): indicate this pin needs a pull up.
	90	MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
	91	Multi-drive is equivalent to open-drain type output.
	92	DEGLITCH (1 << 2): indicate this pin needs deglitch.
	93	PULL_DOWN (1 << 3): indicate this pin needs a pull down.
	94	DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
	95	DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
	96	following values:
	97	00 - No change (reset state value kept)
	98	01 - Low
	99	10 - Medium
	100	11 - High
	101	DEBOUNCE (1 << 16): indicate this pin needs debounce.
	102	DEBOUNCE_VAL (0x3fff << 17): debounce value.
6732ae5c JCPV	103
	104	NOTE:
	105	Some requirements for using atmel,at91rm9200-pinctrl binding:
	106	1. We have pin function node defined under at91 controller node to represent
	107	what pinmux functions this SoC supports.
	108	2. The driver can use the function node's name and pin configuration node's
	109	name describe the pin function and group hierarchy.
	110	For example, Linux at91 pinctrl driver takes the function node's name
	111	as the function name and pin configuration node's name as group name to
	112	create the map table.
	113	3. Each pin configuration node should have a phandle, devices can set pins
	114	configurations by referring to the phandle of that pin configuration node.
	115	4. The gpio controller must be describe in the pinctrl simple-bus.
	116
	117	Examples:
	118
	119	pinctrl@fffff400 {
	120	#address-cells = <1>;
	121	#size-cells = <1>;
	122	ranges;
	123	compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
	124	reg = <0xfffff400 0x600>;
	125
	126	atmel,mux-mask = <
	127	/* A B */
	128	0xffffffff 0xffc00c3b /* pioA */
	129	0xffffffff 0x7fff3ccf /* pioB */
	130	0xffffffff 0x007fffff /* pioC */
	131	>;
	132
	133	/* shared pinctrl settings */
	134	dbgu {
	135	pinctrl_dbgu: dbgu-0 {
	136	atmel,pins =
	137	<1 14 0x1 0x0 /* PB14 periph A */
45976c01	138	1 15 0x1 0x1>; /* PB15 periph A with pullup */
6732ae5c JCPV	139	};
	140	};
	141	};
	142
	143	dbgu: serial@fffff200 {
	144	compatible = "atmel,at91sam9260-usart";
	145	reg = <0xfffff200 0x200>;
	146	interrupts = <1 4 7>;
	147	pinctrl-names = "default";
	148	pinctrl-0 = <&pinctrl_dbgu>;
	149	status = "disabled";
	150	};