Commit | Line | Data |
---|---|---|
ae75ff81 DA |
1 | * Freescale IOMUX Controller (IOMUXC) for i.MX |
2 | ||
3 | The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC | |
4 | to share one PAD to several functional blocks. The sharing is done by | |
5 | multiplexing the PAD input/output signals. For each PAD there are up to | |
6 | 8 muxing options (called ALT modes). Since different modules require | |
7 | different PAD settings (like pull up, keeper, etc) the IOMUXC controls | |
8 | also the PAD settings parameters. | |
9 | ||
10 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
11 | common pinctrl bindings used by client devices, including the meaning of the | |
12 | phrase "pin configuration node". | |
13 | ||
14 | Freescale IMX pin configuration node is a node of a group of pins which can be | |
15 | used for a specific device or function. This node represents both mux and config | |
16 | of the pins in that group. The 'mux' selects the function mode(also named mux | |
17 | mode) this pin can work on and the 'config' configures various pad settings | |
18 | such as pull-up, open drain, drive strength, etc. | |
19 | ||
20 | Required properties for iomux controller: | |
21 | - compatible: "fsl,<soc>-iomuxc" | |
22 | Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. | |
23 | ||
24 | Required properties for pin configuration node: | |
d1c30115 SG |
25 | - fsl,pins: each entry consists of 6 integers and represents the mux and config |
26 | setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val | |
27 | input_val> are specified using a PIN_FUNC_ID macro, which can be found in | |
28 | imx*-pinfunc.h under device tree source folder. The last integer CONFIG is | |
29 | the pad setting value like pull-up on this pin. And that's why fsl,pins entry | |
30 | looks like <PIN_FUNC_ID CONFIG> in the example below. | |
ae75ff81 DA |
31 | |
32 | Bits used for CONFIG: | |
33 | NO_PAD_CTL(1 << 31): indicate this pin does not need config. | |
34 | ||
35 | SION(1 << 30): Software Input On Field. | |
36 | Force the selected mux mode input path no matter of MUX_MODE functionality. | |
37 | By default the input path is determined by functionality of the selected | |
38 | mux mode (regular). | |
39 | ||
40 | Other bits are used for PAD setting. | |
41 | Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part | |
42 | of bits definitions. | |
43 | ||
44 | NOTE: | |
45 | Some requirements for using fsl,imx-pinctrl binding: | |
46 | 1. We have pin function node defined under iomux controller node to represent | |
47 | what pinmux functions this SoC supports. | |
48 | 2. The pin configuration node intends to work on a specific function should | |
49 | to be defined under that specific function node. | |
50 | The function node's name should represent well about what function | |
51 | this group of pins in this pin configuration node are working on. | |
52 | 3. The driver can use the function node's name and pin configuration node's | |
53 | name describe the pin function and group hierarchy. | |
54 | For example, Linux IMX pinctrl driver takes the function node's name | |
55 | as the function name and pin configuration node's name as group name to | |
56 | create the map table. | |
57 | 4. Each pin configuration node should have a phandle, devices can set pins | |
58 | configurations by referring to the phandle of that pin configuration node. | |
59 | ||
60 | Examples: | |
61 | usdhc@0219c000 { /* uSDHC4 */ | |
a04ad043 | 62 | non-removable; |
ae75ff81 DA |
63 | vmmc-supply = <®_3p3v>; |
64 | status = "okay"; | |
65 | pinctrl-names = "default"; | |
66 | pinctrl-0 = <&pinctrl_usdhc4_1>; | |
67 | }; | |
68 | ||
69 | iomuxc@020e0000 { | |
70 | compatible = "fsl,imx6q-iomuxc"; | |
71 | reg = <0x020e0000 0x4000>; | |
72 | ||
73 | /* shared pinctrl settings */ | |
74 | usdhc4 { | |
75 | pinctrl_usdhc4_1: usdhc4grp-1 { | |
d1c30115 SG |
76 | fsl,pins = < |
77 | MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 | |
78 | MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 | |
79 | MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 | |
80 | MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 | |
81 | MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 | |
82 | MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 | |
83 | MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 | |
84 | MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 | |
85 | MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 | |
86 | MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 | |
87 | >; | |
ae75ff81 DA |
88 | }; |
89 | .... | |
90 | }; | |
91 | Refer to the IOMUXC controller chapter in imx6q datasheet, | |
92 | 0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, | |
93 | 80Ohm driver strength and Fast Slew Rate. | |
94 | User should refer to each SoC spec to set the correct value. |