projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
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1 | * Freescale i.MX7 Dual IOMUX Controller |
| 2 | ||
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3 | iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar |
| 4 | as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low | |
| 5 | power state retention capabilities on gpios that are part of iomuxc-lpsr | |
| 6 | (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for | |
| 7 | mux and pad control settings, it shares the input select register from main | |
| 8 | iomuxc controller for daisy chain settings, the fsl,input-sel property extends | |
| 9 | fsl,imx-pinctrl driver to support iomuxc-lpsr controller. | |
| 10 | ||
| 11 | iomuxc_lpsr: iomuxc-lpsr@302c0000 { | |
| 12 | compatible = "fsl,imx7d-iomuxc-lpsr"; | |
| 13 | reg = <0x302c0000 0x10000>; | |
| 14 | fsl,input-sel = <&iomuxc>; | |
| 15 | }; | |
| 16 | ||
| 17 | iomuxc: iomuxc@30330000 { | |
| 18 | compatible = "fsl,imx7d-iomuxc"; | |
| 19 | reg = <0x30330000 0x10000>; | |
| 20 | }; | |
| 21 | ||
| 22 | Pheriparials using pads from iomuxc-lpsr support low state retention power | |
| 23 | state, under LPSR mode GPIO's state of pads are retain. | |
| 24 | ||
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25 | Please refer to fsl,imx-pinctrl.txt in this directory for common binding part |
| 26 | and usage. | |
| 27 | ||
| 28 | Required properties: | |
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29 | - compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or |
| 30 | "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. | |
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31 | - fsl,pins: each entry consists of 6 integers and represents the mux and config |
| 32 | setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val | |
| 33 | input_val> are specified using a PIN_FUNC_ID macro, which can be found in | |
| 34 | imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is | |
| 35 | the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual | |
| 36 | Reference Manual for detailed CONFIG settings. | |
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37 | - fsl,input-sel: required property for iomuxc-lpsr controller, this property is |
| 38 | a phandle for main iomuxc controller which shares the input select register for | |
| 39 | daisy chain settings. | |
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40 | |
| 41 | CONFIG bits definition: | |
| 42 | PAD_CTL_PUS_100K_DOWN (0 << 5) | |
| 43 | PAD_CTL_PUS_5K_UP (1 << 5) | |
| 44 | PAD_CTL_PUS_47K_UP (2 << 5) | |
| 45 | PAD_CTL_PUS_100K_UP (3 << 5) | |
| 46 | PAD_CTL_PUE (1 << 4) | |
| 47 | PAD_CTL_HYS (1 << 3) | |
| 48 | PAD_CTL_SRE_SLOW (1 << 2) | |
| 49 | PAD_CTL_SRE_FAST (0 << 2) | |
| 50 | PAD_CTL_DSE_X1 (0 << 0) | |
| 51 | PAD_CTL_DSE_X2 (1 << 0) | |
| 52 | PAD_CTL_DSE_X3 (2 << 0) | |
| 53 | PAD_CTL_DSE_X4 (3 << 0) | |
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54 | |
| 55 | Examples: | |
| 56 | While iomuxc-lpsr is intended to be used by dedicated peripherals to take | |
| 57 | advantages of LPSR power mode, is also possible that an IP to use pads from | |
| 58 | any of the iomux controllers. For example the I2C1 IP can use SCL pad from | |
| 59 | iomuxc-lpsr controller and SDA pad from iomuxc controller as: | |
| 60 | ||
| 61 | i2c1: i2c@30a20000 { | |
| 62 | pinctrl-names = "default"; | |
| 63 | pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; | |
| 64 | status = "okay"; | |
| 65 | }; | |
| 66 | ||
| 67 | iomuxc-lpsr@302c0000 { | |
| 68 | compatible = "fsl,imx7d-iomuxc-lpsr"; | |
| 69 | reg = <0x302c0000 0x10000>; | |
| 70 | fsl,input-sel = <&iomuxc>; | |
| 71 | ||
| 72 | pinctrl_i2c1_1: i2c1grp-1 { | |
| 73 | fsl,pins = < | |
| 74 | MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f | |
| 75 | >; | |
| 76 | }; | |
| 77 | }; | |
| 78 | ||
| 79 | iomuxc@30330000 { | |
| 80 | compatible = "fsl,imx7d-iomuxc"; | |
| 81 | reg = <0x30330000 0x10000>; | |
| 82 | ||
| 83 | pinctrl_i2c1_2: i2c1grp-2 { | |
| 84 | fsl,pins = < | |
| 85 | MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f | |
| 86 | >; | |
| 87 | }; | |
| 88 | }; |