projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 463e270f TP |
1 | * Marvell Armada XP SoC pinctrl driver for mpp |
| 2 | ||
| 3 | Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding | |
| 4 | part and usage. | |
| 5 | ||
| 6 | Required properties: | |
| 7 | - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", | |
| 8 | "marvell,mv78460-pinctrl" | |
| 356ca6ce | 9 | - reg: register specifier of MPP registers |
| 463e270f TP |
10 | |
| 11 | This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. | |
| 12 | ||
| 13 | Available mpp pins/groups and functions: | |
| 14 | Note: brackets (x) are not part of the mpp name for marvell,function and given | |
| 15 | only for more detailed description in this document. | |
| 16 | ||
| 17 | * Marvell Armada XP (all variants) | |
| 18 | ||
| 19 | name pins functions | |
| 20 | ================================================================================ | |
| 21 | mpp0 0 gpio, ge0(txclko), lcd(d0) | |
| 22 | mpp1 1 gpio, ge0(txd0), lcd(d1) | |
| 23 | mpp2 2 gpio, ge0(txd1), lcd(d2) | |
| 24 | mpp3 3 gpio, ge0(txd2), lcd(d3) | |
| 25 | mpp4 4 gpio, ge0(txd3), lcd(d4) | |
| 26 | mpp5 5 gpio, ge0(txctl), lcd(d5) | |
| 27 | mpp6 6 gpio, ge0(rxd0), lcd(d6) | |
| 28 | mpp7 7 gpio, ge0(rxd1), lcd(d7) | |
| 29 | mpp8 8 gpio, ge0(rxd2), lcd(d8) | |
| 30 | mpp9 9 gpio, ge0(rxd3), lcd(d9) | |
| 31 | mpp10 10 gpio, ge0(rxctl), lcd(d10) | |
| 32 | mpp11 11 gpio, ge0(rxclk), lcd(d11) | |
| 33 | mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12) | |
| 34 | mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13) | |
| 35 | mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15) | |
| 36 | mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16) | |
| 37 | mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16) | |
| 38 | mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17) | |
| 39 | mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) | |
| 40 | mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) | |
| 41 | mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) | |
| 42 | mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) | |
| 43 | mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) | |
| 44 | mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) | |
| 45 | mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) | |
| 46 | mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) | |
| 47 | mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) | |
| 48 | mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) | |
| 49 | mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) | |
| 50 | mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) | |
| 51 | mpp30 30 gpio, tdm(int1), sd0(clk) | |
| 52 | mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) | |
| 53 | mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) | |
| 54 | mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) | |
| 55 | mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) | |
| 56 | mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) | |
| 57 | mpp36 36 gpio, spi(mosi) | |
| 58 | mpp37 37 gpio, spi(miso) | |
| 59 | mpp38 38 gpio, spi(sck) | |
| 60 | mpp39 39 gpio, spi(cs0) | |
| 61 | mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), | |
| 62 | pcie(clkreq0) | |
| 63 | mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), | |
| 64 | pcie(clkreq1) | |
| 65 | mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), | |
| 66 | vdd(cpu0-pd) | |
| 67 | mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), | |
| 68 | vdd(cpu2-3-pd){1} | |
| 69 | mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), | |
| 70 | mem(bat) | |
| 71 | mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) | |
| 72 | mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) | |
| 73 | mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), | |
| 74 | ref(clkout) | |
| 75 | mpp48 48 gpio, tclk, dev(burst/last) | |
| 76 | ||
| 77 | * Marvell Armada XP (mv78260 and mv78460 only) | |
| 78 | ||
| 79 | name pins functions | |
| 80 | ================================================================================ | |
| 81 | mpp49 49 gpio, dev(we3) | |
| 82 | mpp50 50 gpio, dev(we2) | |
| 83 | mpp51 51 gpio, dev(ad16) | |
| 84 | mpp52 52 gpio, dev(ad17) | |
| 85 | mpp53 53 gpio, dev(ad18) | |
| 86 | mpp54 54 gpio, dev(ad19) | |
| 87 | mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) | |
| 88 | mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) | |
| 89 | mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} | |
| 90 | mpp58 58 gpio, dev(ad23) | |
| 91 | mpp59 59 gpio, dev(ad24) | |
| 92 | mpp60 60 gpio, dev(ad25) | |
| 93 | mpp61 61 gpio, dev(ad26) | |
| 94 | mpp62 62 gpio, dev(ad27) | |
| 95 | mpp63 63 gpio, dev(ad28) | |
| 96 | mpp64 64 gpio, dev(ad29) | |
| 97 | mpp65 65 gpio, dev(ad30) | |
| 98 | mpp66 66 gpio, dev(ad31) | |
| 99 | ||
| 100 | Notes: | |
| 101 | * {1} vdd(cpu2-3-pd) only available on mv78460. |