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aeb99c85 NA |
1 | * Oxford Semiconductor OXNAS SoC Family Pin Controller |
2 | ||
3 | Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and | |
4 | ../interrupt-controller/interrupts.txt for generic information regarding | |
5 | pin controller, GPIO, and interrupt bindings. | |
6 | ||
7 | OXNAS 'pin configuration node' is a node of a group of pins which can be | |
8 | used for a specific device or function. This node represents configurations of | |
9 | pins, optional function, and optional mux related configuration. | |
10 | ||
11 | Required properties for pin controller node: | |
12 | - compatible: "oxsemi,ox810se-pinctrl" | |
13 | - oxsemi,sys-ctrl: a phandle to the system controller syscon node | |
14 | ||
15 | Required properties for pin configuration sub-nodes: | |
16 | - pins: List of pins to which the configuration applies. | |
17 | ||
18 | Optional properties for pin configuration sub-nodes: | |
19 | ---------------------------------------------------- | |
20 | - function: Mux function for the specified pins. | |
21 | - bias-pull-up: Enable weak pull-up. | |
22 | ||
23 | Example: | |
24 | ||
25 | pinctrl: pinctrl { | |
26 | compatible = "oxsemi,ox810se-pinctrl"; | |
27 | ||
28 | /* Regmap for sys registers */ | |
29 | oxsemi,sys-ctrl = <&sys>; | |
30 | ||
31 | pinctrl_uart2: pinctrl_uart2 { | |
32 | uart2a { | |
33 | pins = "gpio31"; | |
34 | function = "fct3"; | |
35 | }; | |
36 | uart2b { | |
37 | pins = "gpio32"; | |
38 | function = "fct3"; | |
39 | }; | |
40 | }; | |
41 | }; | |
42 | ||
43 | uart2: serial@900000 { | |
44 | compatible = "ns16550a"; | |
45 | reg = <0x900000 0x100000>; | |
46 | clocks = <&sysclk>; | |
47 | interrupts = <29>; | |
48 | reg-shift = <0>; | |
49 | fifo-size = <16>; | |
50 | reg-io-width = <1>; | |
51 | current-speed = <115200>; | |
52 | no-loopback-test; | |
53 | status = "disabled"; | |
54 | resets = <&reset 22>; | |
55 | pinctrl-names = "default"; | |
56 | pinctrl-0 = <&pinctrl_uart2>; | |
57 | }; |