Commit | Line | Data |
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701016c0 SK |
1 | *ST pin controller. |
2 | ||
3 | Each multi-function pin is controlled, driven and routed through the | |
4 | PIO multiplexing block. Each pin supports GPIO functionality (ALT0) | |
5 | and multiple alternate functions(ALT1 - ALTx) that directly connect | |
6 | the pin to different hardware blocks. | |
7 | ||
8 | When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and | |
9 | Pull Up (PU) are driven by the related PIO block. | |
10 | ||
11 | ST pinctrl driver controls PIO multiplexing block and also interacts with | |
12 | gpio driver to configure a pin. | |
13 | ||
727b0f71 SK |
14 | GPIO bank can have one of the two possible types of interrupt-wirings. |
15 | ||
16 | First type is via irqmux, single interrupt is used by multiple gpio banks. This | |
17 | reduces number of overall interrupts numbers required. All these banks belong to | |
18 | a single pincontroller. | |
19 | _________ | |
20 | | |----> [gpio-bank (n) ] | |
21 | | |----> [gpio-bank (n + 1)] | |
22 | [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] | |
23 | | |----> [gpio-bank (... )] | |
24 | |_________|----> [gpio-bank (n + 7)] | |
25 | ||
26 | Second type has a dedicated interrupt per gpio bank. | |
27 | ||
28 | [irqN]----> [gpio-bank (n)] | |
29 | ||
30 | ||
31 | Pin controller node: | |
32 | Required properties: | |
701016c0 SK |
33 | - compatible : should be "st,<SOC>-<pio-block>-pinctrl" |
34 | like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on. | |
727b0f71 | 35 | - st,syscfg : Should be a phandle of the syscfg node. |
701016c0 SK |
36 | - st,retime-pin-mask : Should be mask to specify which pins can be retimed. |
37 | If the property is not present, it is assumed that all the pins in the | |
38 | bank are capable of retiming. Retiming is mainly used to improve the | |
39 | IO timing margins of external synchronous interfaces. | |
727b0f71 SK |
40 | - ranges : defines mapping between pin controller node (parent) to gpio-bank |
41 | node (children). | |
42 | ||
43 | Optional properties: | |
44 | - interrupts : Interrupt number of the irqmux. If the interrupt is shared | |
45 | with other gpio banks via irqmux. | |
46 | a irqline and gpio banks. | |
47 | - reg : irqmux memory resource. If irqmux is present. | |
48 | - reg-names : irqmux resource should be named as "irqmux". | |
49 | ||
50 | GPIO controller/bank node. | |
51 | Required properties: | |
52 | - gpio-controller : Indicates this device is a GPIO controller | |
53 | - #gpio-cells : Should be one. The first cell is the pin number. | |
54 | - st,bank-name : Should be a name string for this bank as specified in | |
55 | datasheet. | |
56 | ||
57 | Optional properties: | |
58 | - interrupts : Interrupt number for this gpio bank. If there is a dedicated | |
59 | interrupt wired up for this gpio bank. | |
60 | ||
61 | - interrupt-controller : Indicates this device is a interrupt controller. GPIO | |
62 | bank can be an interrupt controller iff one of the interrupt type either via | |
63 | irqmux or a dedicated interrupt per bank is specified. | |
64 | ||
65 | - #interrupt-cells: the value of this property should be 2. | |
66 | - First Cell: represents the external gpio interrupt number local to the | |
67 | gpio interrupt space of the controller. | |
68 | - Second Cell: flags to identify the type of the interrupt | |
69 | - 1 = rising edge triggered | |
70 | - 2 = falling edge triggered | |
71 | - 3 = rising and falling edge triggered | |
72 | - 4 = high level triggered | |
73 | - 8 = low level triggered | |
74 | for related macros look in: | |
75 | include/dt-bindings/interrupt-controller/irq.h | |
701016c0 SK |
76 | |
77 | Example: | |
78 | pin-controller-sbc { | |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
81 | compatible = "st,stih415-sbc-pinctrl"; | |
82 | st,syscfg = <&syscfg_sbc>; | |
727b0f71 SK |
83 | reg = <0xfe61f080 0x4>; |
84 | reg-names = "irqmux"; | |
85 | interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 86 | interrupt-names = "irqmux"; |
701016c0 | 87 | ranges = <0 0xfe610000 0x5000>; |
727b0f71 | 88 | |
701016c0 SK |
89 | PIO0: gpio@fe610000 { |
90 | gpio-controller; | |
91 | #gpio-cells = <1>; | |
727b0f71 SK |
92 | interrupt-controller; |
93 | #interrupt-cells = <2>; | |
701016c0 SK |
94 | reg = <0 0x100>; |
95 | st,bank-name = "PIO0"; | |
96 | }; | |
97 | ... | |
98 | pin-functions nodes follow... | |
99 | }; | |
100 | ||
101 | ||
102 | Contents of function subnode node: | |
103 | ---------------------- | |
104 | Required properties for pin configuration node: | |
105 | - st,pins : Child node with list of pins with configuration. | |
106 | ||
107 | Below is the format of how each pin conf should look like. | |
108 | ||
109 | <bank offset mux mode rt_type rt_delay rt_clk> | |
110 | ||
111 | Every PIO is represented with 4-7 parameters depending on retime configuration. | |
112 | Each parameter is explained as below. | |
113 | ||
114 | -bank : Should be bank phandle to which this PIO belongs. | |
115 | -offset : Offset in the PIO bank. | |
116 | -mux : Should be alternate function number associated this pin. | |
117 | Use same numbers from datasheet. | |
118 | -mode :pin configuration is selected from one of the below values. | |
119 | IN | |
120 | IN_PU | |
121 | OUT | |
122 | BIDIR | |
123 | BIDIR_PU | |
124 | ||
125 | -rt_type Retiming Configuration for the pin. | |
126 | Possible retime configuration are: | |
127 | ||
128 | ------- ------------- | |
129 | value args | |
130 | ------- ------------- | |
131 | NICLK <delay> <clk> | |
132 | ICLK_IO <delay> <clk> | |
133 | BYPASS <delay> | |
134 | DE_IO <delay> <clk> | |
135 | SE_ICLK_IO <delay> <clk> | |
136 | SE_NICLK_IO <delay> <clk> | |
137 | ||
138 | - delay is retime delay in pico seconds as mentioned in data sheet. | |
139 | ||
140 | - rt_clk :clk to be use for retime. | |
141 | Possible values are: | |
142 | CLK_A | |
143 | CLK_B | |
144 | CLK_C | |
145 | CLK_D | |
146 | ||
147 | Example of mmcclk pin which is a bi-direction pull pu with retime config | |
148 | as non inverted clock retimed with CLK_B and delay of 0 pico seconds: | |
149 | ||
150 | pin-controller { | |
151 | ... | |
152 | mmc0 { | |
153 | pinctrl_mmc: mmc { | |
154 | st,pins { | |
155 | mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; | |
156 | ... | |
157 | }; | |
158 | }; | |
159 | ... | |
160 | }; | |
161 | }; | |
162 | ||
163 | sdhci0:sdhci@fe810000{ | |
164 | ... | |
727b0f71 SK |
165 | interrupt-parent = <&PIO3>; |
166 | #interrupt-cells = <2>; | |
167 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ | |
ae107d06 | 168 | interrupt-names = "card-detect"; |
701016c0 SK |
169 | pinctrl-names = "default"; |
170 | pinctrl-0 = <&pinctrl_mmc>; | |
171 | }; |