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1 | Qualcomm APQ8064 TLMM block |
2 | ||
3 | Required properties: | |
4 | - compatible: "qcom,apq8064-pinctrl" | |
5 | - reg: Should be the base address and length of the TLMM block. | |
6 | - interrupts: Should be the parent IRQ of the TLMM block. | |
7 | - interrupt-controller: Marks the device node as an interrupt controller. | |
8 | - #interrupt-cells: Should be two. | |
9 | - gpio-controller: Marks the device node as a GPIO controller. | |
10 | - #gpio-cells : Should be two. | |
11 | The first cell is the gpio pin number and the | |
12 | second cell is used for optional parameters. | |
13 | ||
14 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | |
15 | a general description of GPIO and interrupt bindings. | |
16 | ||
17 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
18 | common pinctrl bindings used by client devices, including the meaning of the | |
19 | phrase "pin configuration node". | |
20 | ||
a0e27f51 | 21 | Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
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22 | subnodes. Each of these subnodes represents some desired configuration for a |
23 | pin, a group, or a list of pins or groups. This configuration can include the | |
24 | mux function to select on those pin(s)/group(s), and various pin configuration | |
25 | parameters, such as pull-up, drive strength, etc. | |
26 | ||
27 | The name of each subnode is not important; all subnodes should be enumerated | |
28 | and processed purely based on their content. | |
29 | ||
30 | Each subnode only affects those parameters that are explicitly listed. In | |
31 | other words, a subnode that lists a mux function but no pin configuration | |
32 | parameters implies no information about any pin configuration parameters. | |
33 | Similarly, a pin subnode that describes a pullup parameter implies no | |
34 | information about e.g. the mux function. | |
35 | ||
36 | ||
37 | The following generic properties as defined in pinctrl-bindings.txt are valid | |
38 | to specify in a pin configuration subnode: | |
39 | ||
40 | pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength, | |
41 | output-low, output-high. | |
42 | ||
43 | Non-empty subnodes must specify the 'pins' property. | |
44 | ||
45 | Valid values for pins are: | |
46 | gpio0-gpio89 | |
47 | ||
48 | Valid values for function are: | |
144ef626 | 49 | cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4, |
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50 | gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, |
51 | gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, | |
52 | gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, | |
79c62cdd | 53 | riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold |
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54 | |
55 | Example: | |
56 | ||
57 | msmgpio: pinctrl@800000 { | |
58 | compatible = "qcom,apq8064-pinctrl"; | |
59 | reg = <0x800000 0x4000>; | |
60 | ||
61 | gpio-controller; | |
62 | #gpio-cells = <2>; | |
63 | interrupt-controller; | |
64 | #interrupt-cells = <2>; | |
0252d6a2 | 65 | interrupts = <0 16 0x4>; |
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66 | |
67 | pinctrl-names = "default"; | |
68 | pinctrl-0 = <&gsbi5_uart_default>; | |
69 | ||
70 | gsbi5_uart_default: gsbi5_uart_default { | |
71 | mux { | |
72 | pins = "gpio51", "gpio52"; | |
73 | function = "gsbi5"; | |
74 | }; | |
75 | ||
76 | tx { | |
77 | pins = "gpio51"; | |
78 | drive-strength = <4>; | |
79 | bias-disable; | |
80 | }; | |
81 | ||
82 | rx { | |
83 | pins = "gpio52"; | |
84 | drive-strength = <2>; | |
85 | bias-pull-up; | |
86 | }; | |
87 | }; | |
88 | }; |