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fe1c9a82 LP |
1 | * Renesas Pin Function Controller (GPIO and Pin Mux/Config) |
2 | ||
3 | The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372, | |
4 | SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller. | |
5 | ||
6 | ||
7 | Pin Control | |
8 | ----------- | |
9 | ||
10 | Required Properties: | |
11 | ||
12 | - compatible: should be one of the following. | |
13 | - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. | |
14 | - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. | |
15 | - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. | |
16 | - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. | |
17 | - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. | |
18 | - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller. | |
19 | - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. | |
20 | ||
21 | - reg: Base address and length of each memory resource used by the pin | |
22 | controller hardware module. | |
23 | ||
24 | Optional properties: | |
25 | ||
26 | - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden | |
27 | otherwise. Should be 3. | |
28 | ||
70c8f01a LP |
29 | - interrupts-extended: Specify the interrupts associated with external |
30 | IRQ pins. This property is mandatory when the PFC handles GPIOs and | |
31 | forbidden otherwise. When specified, it must contain one interrupt per | |
32 | external IRQ, sorted by external IRQ number. | |
33 | ||
fe1c9a82 LP |
34 | The PFC node also acts as a container for pin configuration nodes. Please refer |
35 | to pinctrl-bindings.txt in this directory for the definition of the term "pin | |
36 | configuration node" and for the common pinctrl bindings used by client devices. | |
37 | ||
12f3ad8d LP |
38 | Each pin configuration node represents a desired configuration for a pin, a |
39 | pin group, or a list of pins or pin groups. The configuration can include the | |
40 | function to select on those pin(s) and pin configuration parameters (such as | |
41 | pull-up and pull-down). | |
fe1c9a82 | 42 | |
12f3ad8d LP |
43 | Pin configuration nodes contain pin configuration properties, either directly |
44 | or grouped in child subnodes. Both pin muxing and configuration parameters can | |
45 | be grouped in that way and referenced as a single pin configuration node by | |
46 | client devices. | |
47 | ||
48 | A configuration node or subnode must reference at least one pin (through the | |
49 | pins or pin groups properties) and contain at least a function or one | |
50 | configuration parameter. When the function is present only pin groups can be | |
51 | used to reference pins. | |
fe1c9a82 LP |
52 | |
53 | All pin configuration nodes and subnodes names are ignored. All of those nodes | |
54 | are parsed through phandles and processed purely based on their content. | |
55 | ||
56 | Pin Configuration Node Properties: | |
57 | ||
12f3ad8d | 58 | - renesas,pins : An array of strings, each string containing the name of a pin. |
fe1c9a82 LP |
59 | - renesas,groups : An array of strings, each string containing the name of a pin |
60 | group. | |
61 | ||
62 | - renesas,function: A string containing the name of the function to mux to the | |
63 | pin group(s) specified by the renesas,groups property | |
64 | ||
65 | Valid values for pin, group and function names can be found in the group and | |
66 | function arrays of the PFC data file corresponding to the SoC | |
67 | (drivers/pinctrl/sh-pfc/pfc-*.c) | |
68 | ||
12f3ad8d LP |
69 | The pin configuration parameters use the generic pinconf bindings defined in |
70 | pinctrl-bindings.txt in this directory. The supported parameters are | |
71 | bias-disable, bias-pull-up and bias-pull-down. | |
72 | ||
fe1c9a82 LP |
73 | |
74 | GPIO | |
75 | ---- | |
76 | ||
77 | On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller | |
78 | node. | |
79 | ||
80 | Required Properties: | |
81 | ||
82 | - gpio-controller: Marks the device node as a gpio controller. | |
83 | ||
84 | - #gpio-cells: Should be 2. The first cell is the GPIO number and the second | |
85 | cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the | |
86 | GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. | |
87 | ||
88 | The syntax of the gpio specifier used by client nodes should be the following | |
89 | with values derived from the SoC user manual. | |
90 | ||
91 | <[phandle of the gpio controller node] | |
92 | [pin number within the gpio controller] | |
93 | [flags]> | |
94 | ||
95 | On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. | |
96 | Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | |
97 | for documentation of the GPIO device tree bindings on those platforms. | |
98 | ||
99 | ||
100 | Examples | |
101 | -------- | |
102 | ||
103 | Example 1: SH73A0 (SH-Mobile AG5) pin controller node | |
104 | ||
105 | pfc: pfc@e6050000 { | |
106 | compatible = "renesas,pfc-sh73a0"; | |
107 | reg = <0xe6050000 0x8000>, | |
108 | <0xe605801c 0x1c>; | |
109 | gpio-controller; | |
110 | #gpio-cells = <2>; | |
70c8f01a LP |
111 | interrupts-extended = |
112 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
113 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
114 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
115 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
116 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
117 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
118 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
119 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
fe1c9a82 LP |
120 | }; |
121 | ||
122 | Example 2: A GPIO LED node that references a GPIO | |
123 | ||
124 | #include <dt-bindings/gpio/gpio.h> | |
125 | ||
126 | leds { | |
127 | compatible = "gpio-leds"; | |
128 | led1 { | |
129 | gpios = <&pfc 20 GPIO_ACTIVE_LOW>; | |
130 | }; | |
131 | }; | |
132 | ||
133 | Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps | |
134 | for the MMCIF and SCIFA4 devices | |
135 | ||
136 | &pfc { | |
137 | pinctrl-0 = <&scifa4_pins>; | |
138 | pinctrl-names = "default"; | |
139 | ||
140 | mmcif_pins: mmcif { | |
12f3ad8d LP |
141 | mux { |
142 | renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; | |
143 | renesas,function = "mmc0"; | |
144 | }; | |
145 | cfg { | |
146 | renesas,groups = "mmc0_data8_0"; | |
147 | renesas,pins = "PORT279"; | |
148 | bias-pull-up; | |
149 | }; | |
fe1c9a82 LP |
150 | }; |
151 | ||
152 | scifa4_pins: scifa4 { | |
153 | renesas,groups = "scifa4_data", "scifa4_ctrl"; | |
154 | renesas,function = "scifa4"; | |
155 | }; | |
156 | }; | |
157 | ||
158 | Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device | |
159 | ||
160 | &mmcif { | |
161 | pinctrl-0 = <&mmcif_pins>; | |
162 | pinctrl-names = "default"; | |
163 | ||
164 | bus-width = <8>; | |
165 | vmmc-supply = <®_1p8v>; | |
166 | status = "okay"; | |
167 | }; |