Commit | Line | Data |
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d3e51161 HS |
1 | * Rockchip Pinmux Controller |
2 | ||
3 | The Rockchip Pinmux Controller, enables the IC | |
4 | to share one PAD to several functional blocks. The sharing is done by | |
5 | multiplexing the PAD input/output signals. For each PAD there are up to | |
6 | 4 muxing options with option 0 being the use as a GPIO. | |
7 | ||
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
9 | common pinctrl bindings used by client devices, including the meaning of the | |
10 | phrase "pin configuration node". | |
11 | ||
12 | The Rockchip pin configuration node is a node of a group of pins which can be | |
13 | used for a specific device or function. This node represents both mux and | |
14 | config of the pins in that group. The 'pins' selects the function mode(also | |
15 | named pin mode) this pin can work on and the 'config' configures various pad | |
16 | settings such as pull-up, etc. | |
17 | ||
18 | The pins are grouped into up to 5 individual pin banks which need to be | |
19 | defined as gpio sub-nodes of the pinmux controller. | |
20 | ||
21 | Required properties for iomux controller: | |
22 | - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" | |
23 | "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" | |
c51426ef HS |
24 | - rockchip,grf: phandle referencing a syscon providing the |
25 | "general register files" | |
26 | ||
27 | Optional properties for iomux controller: | |
28 | - rockchip,pmu: phandle referencing a syscon providing the pmu registers | |
29 | as some SoCs carry parts of the iomux controller registers there. | |
30 | Required for at least rk3188 and rk3288. | |
31 | ||
32 | Deprecated properties for iomux controller: | |
6ca5274d | 33 | - reg: first element is the general register space of the iomux controller |
bfc7a42a | 34 | It should be large enough to contain also separate pull registers. |
c51426ef HS |
35 | second element is the separate pull register space of the rk3188. |
36 | Use rockchip,grf and rockchip,pmu described above instead. | |
d3e51161 HS |
37 | |
38 | Required properties for gpio sub nodes: | |
fc72c923 | 39 | - compatible: "rockchip,gpio-bank" |
d3e51161 HS |
40 | - reg: register of the gpio bank (different than the iomux registerset) |
41 | - interrupts: base interrupt of the gpio bank in the interrupt controller | |
42 | - clocks: clock that drives this bank | |
43 | - gpio-controller: identifies the node as a gpio controller and pin bank. | |
44 | - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO | |
45 | binding is used, the amount of cells must be specified as 2. See generic | |
46 | GPIO binding documentation for description of particular cells. | |
47 | - interrupt-controller: identifies the controller node as interrupt-parent. | |
48 | - #interrupt-cells: the value of this property should be 2 and the interrupt | |
49 | cells should use the standard two-cell scheme described in | |
50 | bindings/interrupt-controller/interrupts.txt | |
51 | ||
c51426ef | 52 | Deprecated properties for gpio sub nodes: |
fc72c923 | 53 | - compatible: "rockchip,rk3188-gpio-bank0" |
c51426ef HS |
54 | - reg: second element: separate pull register for rk3188 bank0, use |
55 | rockchip,pmu described above instead | |
56 | ||
d3e51161 HS |
57 | Required properties for pin configuration node: |
58 | - rockchip,pins: 3 integers array, represents a group of pins mux and config | |
59 | setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. | |
60 | The MUX 0 means gpio and MUX 1 to 3 mean the specific device function. | |
61 | The phandle of a node containing the generic pinconfig options | |
62 | to use, as described in pinctrl-bindings.txt in this directory. | |
63 | ||
64 | Examples: | |
65 | ||
66 | #include <dt-bindings/pinctrl/rockchip.h> | |
67 | ||
68 | ... | |
69 | ||
70 | pinctrl@20008000 { | |
71 | compatible = "rockchip,rk3066a-pinctrl"; | |
c51426ef HS |
72 | rockchip,grf = <&grf>; |
73 | ||
d3e51161 HS |
74 | #address-cells = <1>; |
75 | #size-cells = <1>; | |
76 | ranges; | |
77 | ||
78 | gpio0: gpio0@20034000 { | |
79 | compatible = "rockchip,gpio-bank"; | |
80 | reg = <0x20034000 0x100>; | |
81 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
82 | clocks = <&clk_gates8 9>; | |
83 | ||
84 | gpio-controller; | |
85 | #gpio-cells = <2>; | |
86 | ||
87 | interrupt-controller; | |
88 | #interrupt-cells = <2>; | |
89 | }; | |
90 | ||
91 | ... | |
92 | ||
93 | pcfg_pull_default: pcfg_pull_default { | |
94 | bias-pull-pin-default | |
95 | }; | |
96 | ||
97 | uart2 { | |
98 | uart2_xfer: uart2-xfer { | |
99 | rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, | |
100 | <RK_GPIO1 9 1 &pcfg_pull_default>; | |
101 | }; | |
102 | }; | |
103 | }; | |
104 | ||
105 | uart2: serial@20064000 { | |
106 | compatible = "snps,dw-apb-uart"; | |
107 | reg = <0x20064000 0x400>; | |
108 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
109 | reg-shift = <2>; | |
110 | reg-io-width = <1>; | |
111 | clocks = <&mux_uart2>; | |
112 | status = "okay"; | |
113 | ||
114 | pinctrl-names = "default"; | |
115 | pinctrl-0 = <&uart2_xfer>; | |
116 | }; | |
6ca5274d HS |
117 | |
118 | Example for rk3188: | |
119 | ||
120 | pinctrl@20008000 { | |
121 | compatible = "rockchip,rk3188-pinctrl"; | |
c51426ef HS |
122 | rockchip,grf = <&grf>; |
123 | rockchip,pmu = <&pmu>; | |
6ca5274d HS |
124 | #address-cells = <1>; |
125 | #size-cells = <1>; | |
126 | ranges; | |
127 | ||
128 | gpio0: gpio0@0x2000a000 { | |
129 | compatible = "rockchip,rk3188-gpio-bank0"; | |
c51426ef | 130 | reg = <0x2000a000 0x100>; |
6ca5274d HS |
131 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
132 | clocks = <&clk_gates8 9>; | |
133 | ||
134 | gpio-controller; | |
135 | #gpio-cells = <2>; | |
136 | ||
137 | interrupt-controller; | |
138 | #interrupt-cells = <2>; | |
139 | }; | |
140 | ||
141 | gpio1: gpio1@0x2003c000 { | |
142 | compatible = "rockchip,gpio-bank"; | |
143 | reg = <0x2003c000 0x100>; | |
144 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
145 | clocks = <&clk_gates8 10>; | |
146 | ||
147 | gpio-controller; | |
148 | #gpio-cells = <2>; | |
149 | ||
150 | interrupt-controller; | |
151 | #interrupt-cells = <2>; | |
152 | }; | |
153 | ||
154 | ... | |
155 | ||
156 | }; |