Commit | Line | Data |
---|---|---|
64a45c98 PC |
1 | ST Ericsson abx500 pinmux controller |
2 | ||
3 | Required properties: | |
4 | - compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio", | |
5 | "stericsson,ab8505-gpio", "stericsson,ab9540-gpio", | |
6 | ||
7 | Please refer to pinctrl-bindings.txt in this directory for details of the | |
8 | common pinctrl bindings used by client devices, including the meaning of the | |
9 | phrase "pin configuration node". | |
10 | ||
4944d2ca LW |
11 | ST Ericsson's pin configuration nodes use the generic pin multiplexing |
12 | and pin configuration bindings, see pinctrl-bindings.txt | |
64a45c98 PC |
13 | |
14 | Example board file extract: | |
15 | ||
16 | &pinctrl_abx500 { | |
17 | pinctrl-names = "default"; | |
18 | pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>; | |
19 | ||
20 | sysclkreq2 { | |
21 | sysclkreq2_default_mode: sysclkreq2_default { | |
22 | default_mux { | |
4944d2ca LW |
23 | function = "sysclkreq"; |
24 | groups = "sysclkreq2_d_1"; | |
64a45c98 PC |
25 | }; |
26 | default_cfg { | |
4944d2ca | 27 | pins = "GPIO1"; |
64a45c98 PC |
28 | bias-disable; |
29 | }; | |
30 | }; | |
31 | }; | |
32 | sysclkreq3 { | |
33 | sysclkreq3_default_mode: sysclkreq3_default { | |
34 | default_mux { | |
4944d2ca LW |
35 | function = "sysclkreq"; |
36 | groups = "sysclkreq3_d_1"; | |
64a45c98 PC |
37 | }; |
38 | default_cfg { | |
4944d2ca | 39 | pins = "GPIO2"; |
64a45c98 PC |
40 | output-low; |
41 | }; | |
42 | }; | |
43 | }; | |
44 | gpio3 { | |
45 | gpio3_default_mode: gpio3_default { | |
46 | default_mux { | |
4944d2ca LW |
47 | function = "gpio"; |
48 | groups = "gpio3_a_1"; | |
64a45c98 PC |
49 | }; |
50 | default_cfg { | |
4944d2ca | 51 | pins = "GPIO3"; |
64a45c98 PC |
52 | output-low; |
53 | }; | |
54 | }; | |
55 | }; | |
56 | sysclkreq6 { | |
57 | sysclkreq6_default_mode: sysclkreq6_default { | |
58 | default_mux { | |
4944d2ca LW |
59 | function = "sysclkreq"; |
60 | groups = "sysclkreq6_d_1"; | |
64a45c98 PC |
61 | }; |
62 | default_cfg { | |
4944d2ca | 63 | pins = "GPIO4"; |
64a45c98 PC |
64 | bias-disable; |
65 | }; | |
66 | }; | |
67 | }; | |
68 | pwmout1 { | |
69 | pwmout1_default_mode: pwmout1_default { | |
70 | default_mux { | |
4944d2ca LW |
71 | function = "pwmout"; |
72 | groups = "pwmout1_d_1"; | |
64a45c98 PC |
73 | }; |
74 | default_cfg { | |
4944d2ca | 75 | pins = "GPIO14"; |
64a45c98 PC |
76 | output-low; |
77 | }; | |
78 | }; | |
79 | }; | |
80 | pwmout2 { | |
81 | pwmout2_default_mode: pwmout2_default { | |
82 | pwmout2_default_mux { | |
4944d2ca LW |
83 | function = "pwmout"; |
84 | groups = "pwmout2_d_1"; | |
64a45c98 PC |
85 | }; |
86 | pwmout2_default_cfg { | |
4944d2ca | 87 | pins = "GPIO15"; |
64a45c98 PC |
88 | output-low; |
89 | }; | |
90 | }; | |
91 | }; | |
92 | pwmout3 { | |
93 | pwmout3_default_mode: pwmout3_default { | |
94 | pwmout3_default_mux { | |
4944d2ca LW |
95 | function = "pwmout"; |
96 | groups = "pwmout3_d_1"; | |
64a45c98 PC |
97 | }; |
98 | pwmout3_default_cfg { | |
4944d2ca | 99 | pins = "GPIO16"; |
64a45c98 PC |
100 | output-low; |
101 | }; | |
102 | }; | |
103 | }; | |
104 | adi1 { | |
105 | ||
106 | adi1_default_mode: adi1_default { | |
107 | adi1_default_mux { | |
4944d2ca LW |
108 | function = "adi1"; |
109 | groups = "adi1_d_1"; | |
64a45c98 PC |
110 | }; |
111 | adi1_default_cfg1 { | |
4944d2ca | 112 | pins = "GPIO17","GPIO19","GPIO20"; |
64a45c98 PC |
113 | bias-disable; |
114 | }; | |
115 | adi1_default_cfg2 { | |
4944d2ca | 116 | pins = "GPIO18"; |
64a45c98 PC |
117 | output-low; |
118 | }; | |
119 | }; | |
120 | }; | |
121 | dmic12 { | |
122 | dmic12_default_mode: dmic12_default { | |
123 | dmic12_default_mux { | |
4944d2ca LW |
124 | function = "dmic"; |
125 | groups = "dmic12_d_1"; | |
64a45c98 PC |
126 | }; |
127 | dmic12_default_cfg1 { | |
4944d2ca | 128 | pins = "GPIO27"; |
64a45c98 PC |
129 | output-low; |
130 | }; | |
131 | dmic12_default_cfg2 { | |
4944d2ca | 132 | pins = "GPIO28"; |
64a45c98 PC |
133 | bias-disable; |
134 | }; | |
135 | }; | |
136 | }; | |
137 | dmic34 { | |
138 | dmic34_default_mode: dmic34_default { | |
139 | dmic34_default_mux { | |
4944d2ca LW |
140 | function = "dmic"; |
141 | groups = "dmic34_d_1"; | |
64a45c98 PC |
142 | }; |
143 | dmic34_default_cfg1 { | |
4944d2ca | 144 | pins = "GPIO29"; |
64a45c98 PC |
145 | output-low; |
146 | }; | |
147 | dmic34_default_cfg2 { | |
4944d2ca | 148 | pins = "GPIO30"; |
64a45c98 PC |
149 | bias-disable;{ |
150 | ||
151 | }; | |
152 | }; | |
153 | }; | |
154 | dmic56 { | |
155 | dmic56_default_mode: dmic56_default { | |
156 | dmic56_default_mux { | |
4944d2ca LW |
157 | function = "dmic"; |
158 | groups = "dmic56_d_1"; | |
64a45c98 PC |
159 | }; |
160 | dmic56_default_cfg1 { | |
4944d2ca | 161 | pins = "GPIO31"; |
64a45c98 PC |
162 | output-low; |
163 | }; | |
164 | dmic56_default_cfg2 { | |
4944d2ca | 165 | pins = "GPIO32"; |
64a45c98 PC |
166 | bias-disable; |
167 | }; | |
168 | }; | |
169 | }; | |
170 | sysclkreq5 { | |
171 | sysclkreq5_default_mode: sysclkreq5_default { | |
172 | sysclkreq5_default_mux { | |
4944d2ca LW |
173 | function = "sysclkreq"; |
174 | groups = "sysclkreq5_d_1"; | |
64a45c98 PC |
175 | }; |
176 | sysclkreq5_default_cfg { | |
4944d2ca | 177 | pins = "GPIO42"; |
64a45c98 PC |
178 | output-low; |
179 | }; | |
180 | }; | |
181 | }; | |
182 | batremn { | |
183 | batremn_default_mode: batremn_default { | |
184 | batremn_default_mux { | |
4944d2ca LW |
185 | function = "batremn"; |
186 | groups = "batremn_d_1"; | |
64a45c98 PC |
187 | }; |
188 | batremn_default_cfg { | |
4944d2ca | 189 | pins = "GPIO43"; |
64a45c98 PC |
190 | bias-disable; |
191 | }; | |
192 | }; | |
193 | }; | |
194 | service { | |
195 | service_default_mode: service_default { | |
196 | service_default_mux { | |
4944d2ca LW |
197 | function = "service"; |
198 | groups = "service_d_1"; | |
64a45c98 PC |
199 | }; |
200 | service_default_cfg { | |
4944d2ca | 201 | pins = "GPIO44"; |
64a45c98 PC |
202 | bias-disable; |
203 | }; | |
204 | }; | |
205 | }; | |
206 | pwrctrl0 { | |
207 | pwrctrl0_default_mux: pwrctrl0_mux { | |
208 | pwrctrl0_default_mux { | |
4944d2ca LW |
209 | function = "pwrctrl"; |
210 | groups = "pwrctrl0_d_1"; | |
64a45c98 PC |
211 | }; |
212 | }; | |
213 | pwrctrl0_default_mode: pwrctrl0_default { | |
214 | pwrctrl0_default_cfg { | |
4944d2ca | 215 | pins = "GPIO45"; |
64a45c98 PC |
216 | bias-disable; |
217 | }; | |
218 | }; | |
219 | }; | |
220 | pwrctrl1 { | |
221 | pwrctrl1_default_mux: pwrctrl1_mux { | |
222 | pwrctrl1_default_mux { | |
4944d2ca LW |
223 | function = "pwrctrl"; |
224 | groups = "pwrctrl1_d_1"; | |
64a45c98 PC |
225 | }; |
226 | }; | |
227 | pwrctrl1_default_mode: pwrctrl1_default { | |
228 | pwrctrl1_default_cfg { | |
4944d2ca | 229 | pins = "GPIO46"; |
64a45c98 PC |
230 | bias-disable; |
231 | }; | |
232 | }; | |
233 | }; | |
234 | pwmextvibra1 { | |
235 | pwmextvibra1_default_mode: pwmextvibra1_default { | |
236 | pwmextvibra1_default_mux { | |
4944d2ca LW |
237 | function = "pwmextvibra"; |
238 | groups = "pwmextvibra1_d_1"; | |
64a45c98 PC |
239 | }; |
240 | pwmextvibra1_default_cfg { | |
4944d2ca | 241 | pins = "GPIO47"; |
64a45c98 PC |
242 | bias-disable; |
243 | }; | |
244 | }; | |
245 | }; | |
246 | pwmextvibra2 { | |
247 | pwmextvibra2_default_mode: pwmextvibra2_default { | |
248 | pwmextvibra2_default_mux { | |
4944d2ca LW |
249 | function = "pwmextvibra"; |
250 | groups = "pwmextvibra2_d_1"; | |
64a45c98 PC |
251 | }; |
252 | pwmextvibra1_default_cfg { | |
4944d2ca | 253 | pins = "GPIO48"; |
64a45c98 PC |
254 | bias-disable; |
255 | }; | |
256 | }; | |
257 | }; | |
258 | gpio51 { | |
259 | gpio51_default_mode: gpio51_default { | |
260 | gpio51_default_mux { | |
4944d2ca LW |
261 | function = "gpio"; |
262 | groups = "gpio51_a_1"; | |
64a45c98 PC |
263 | }; |
264 | gpio51_default_cfg { | |
4944d2ca | 265 | pins = "GPIO51"; |
64a45c98 PC |
266 | output-low; |
267 | }; | |
268 | }; | |
269 | }; | |
270 | gpio52 { | |
271 | gpio52_default_mode: gpio52_default { | |
272 | gpio52_default_mux { | |
4944d2ca LW |
273 | function = "gpio"; |
274 | groups = "gpio52_a_1"; | |
64a45c98 PC |
275 | }; |
276 | gpio52_default_cfg { | |
4944d2ca | 277 | pins = "GPIO52"; |
64a45c98 PC |
278 | bias-pull-down; |
279 | }; | |
280 | }; | |
281 | }; | |
282 | gpio53 { | |
283 | gpio53_default_mode: gpio53_default { | |
284 | gpio53_default_mux { | |
4944d2ca LW |
285 | function = "gpio"; |
286 | groups = "gpio53_a_1"; | |
64a45c98 PC |
287 | }; |
288 | gpio53_default_cfg { | |
4944d2ca | 289 | pins = "GPIO53"; |
64a45c98 PC |
290 | bias-pull-down; |
291 | }; | |
292 | }; | |
293 | }; | |
294 | gpio54 { | |
295 | gpio54_default_mode: gpio54_default { | |
296 | gpio54_default_mux { | |
4944d2ca LW |
297 | function = "gpio"; |
298 | groups = "gpio54_a_1"; | |
64a45c98 PC |
299 | }; |
300 | gpio54_default_cfg { | |
4944d2ca | 301 | pins = "GPIO54"; |
64a45c98 PC |
302 | output-low; |
303 | }; | |
304 | }; | |
305 | }; | |
306 | pdmclkdat { | |
307 | pdmclkdat_default_mode: pdmclkdat_default { | |
308 | pdmclkdat_default_mux { | |
4944d2ca LW |
309 | function = "pdm"; |
310 | groups = "pdmclkdat_d_1"; | |
64a45c98 PC |
311 | }; |
312 | pdmclkdat_default_cfg { | |
4944d2ca | 313 | pins = "GPIO55", "GPIO56"; |
64a45c98 PC |
314 | bias-disable; |
315 | }; | |
316 | }; | |
317 | }; | |
318 | }; |