Commit | Line | Data |
---|---|---|
140fd977 TR |
1 | Tegra SoC PWFM controller |
2 | ||
3 | Required properties: | |
57dfd17e LD |
4 | - compatible: Must be: |
5 | - "nvidia,tegra20-pwm": for Tegra20 | |
6 | - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30 | |
7 | - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114 | |
8 | - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124 | |
9 | - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132 | |
10 | - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210 | |
11 | - "nvidia,tegra186-pwm": for Tegra186 | |
140fd977 | 12 | - reg: physical base address and length of the controller's registers |
ebeec0af LP |
13 | - #pwm-cells: should be 2. See pwm.txt in this directory for a description of |
14 | the cells format. | |
d8f64797 SW |
15 | - clocks: Must contain one entry, for the module clock. |
16 | See ../clocks/clock-bindings.txt for details. | |
07999587 SW |
17 | - resets: Must contain an entry for each entry in reset-names. |
18 | See ../reset/reset.txt for details. | |
19 | - reset-names: Must include the following entries: | |
20 | - pwm | |
140fd977 TR |
21 | |
22 | Example: | |
23 | ||
24 | pwm: pwm@7000a000 { | |
25 | compatible = "nvidia,tegra20-pwm"; | |
26 | reg = <0x7000a000 0x100>; | |
27 | #pwm-cells = <2>; | |
d8f64797 | 28 | clocks = <&tegra_car 17>; |
07999587 SW |
29 | resets = <&tegra_car 17>; |
30 | reset-names = "pwm"; | |
140fd977 | 31 | }; |