Commit | Line | Data |
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5b5ff97d TF |
1 | * Samsung PWM timers |
2 | ||
3 | Samsung SoCs contain PWM timer blocks which can be used for system clock source | |
4 | and clock event timers, as well as to drive SoC outputs with PWM signal. Each | |
5 | PWM timer block provides 5 PWM channels (not all of them can drive physical | |
6 | outputs - see SoC and board manual). | |
7 | ||
8 | Be aware that the clocksource driver supports only uniprocessor systems. | |
9 | ||
10 | Required properties: | |
11 | - compatible : should be one of following: | |
12 | samsung,s3c2410-pwm - for 16-bit timers present on S3C24xx SoCs | |
13 | samsung,s3c6400-pwm - for 32-bit timers present on S3C64xx SoCs | |
14 | samsung,s5p6440-pwm - for 32-bit timers present on S5P64x0 SoCs | |
15 | samsung,s5pc100-pwm - for 32-bit timers present on S5PC100, S5PV210, | |
16 | Exynos4210 rev0 SoCs | |
17 | samsung,exynos4210-pwm - for 32-bit timers present on Exynos4210, | |
18 | Exynos4x12 and Exynos5250 SoCs | |
19 | - reg: base address and size of register area | |
20 | - interrupts: list of timer interrupts (one interrupt per timer, starting at | |
21 | timer 0) | |
ebeec0af LP |
22 | - #pwm-cells: should be 3. See pwm.txt in this directory for a description of |
23 | the cells format. The only third cell flag supported by this binding is | |
24 | PWM_POLARITY_INVERTED. | |
5b5ff97d TF |
25 | |
26 | Optional properties: | |
27 | - samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular | |
28 | platform - an array of up to 5 elements being indices of PWM channels | |
29 | (from 0 to 4), the order does not matter. | |
30 | ||
31 | Example: | |
32 | pwm@7f006000 { | |
33 | compatible = "samsung,s3c6400-pwm"; | |
34 | reg = <0x7f006000 0x1000>; | |
35 | interrupt-parent = <&vic0>; | |
36 | interrupts = <23>, <24>, <25>, <27>, <28>; | |
37 | samsung,pwm-outputs = <0>, <1>; | |
38 | #pwm-cells = <3>; | |
39 | } |