Commit | Line | Data |
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02985b94 PZ |
1 | Freescale i.MX System Reset Controller |
2 | ====================================== | |
3 | ||
4 | Please also refer to reset.txt in this directory for common reset | |
5 | controller binding usage. | |
6 | ||
7 | Required properties: | |
8 | - compatible: Should be "fsl,<chip>-src" | |
9 | - reg: should be register base and length as documented in the | |
10 | datasheet | |
11 | - interrupts: Should contain SRC interrupt and CPU WDOG interrupt, | |
12 | in this order. | |
13 | - #reset-cells: 1, see below | |
14 | ||
15 | example: | |
16 | ||
17 | src: src@020d8000 { | |
18 | compatible = "fsl,imx6q-src"; | |
19 | reg = <0x020d8000 0x4000>; | |
20 | interrupts = <0 91 0x04 0 96 0x04>; | |
21 | #reset-cells = <1>; | |
22 | }; | |
23 | ||
24 | Specifying reset lines connected to IP modules | |
25 | ============================================== | |
26 | ||
27 | The system reset controller can be used to reset the GPU, VPU, | |
28 | IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device | |
29 | nodes should specify the reset line on the SRC in their resets | |
30 | property, containing a phandle to the SRC device node and a | |
31 | RESET_INDEX specifying which module to reset, as described in | |
32 | reset.txt | |
33 | ||
34 | example: | |
35 | ||
36 | ipu1: ipu@02400000 { | |
37 | resets = <&src 2>; | |
38 | }; | |
39 | ipu2: ipu@02800000 { | |
40 | resets = <&src 4>; | |
41 | }; | |
42 | ||
43 | The following RESET_INDEX values are valid for i.MX5: | |
44 | GPU_RESET 0 | |
45 | VPU_RESET 1 | |
46 | IPU1_RESET 2 | |
47 | OPEN_VG_RESET 3 | |
48 | The following additional RESET_INDEX value is valid for i.MX6: | |
49 | IPU2_RESET 4 |