Commit | Line | Data |
---|---|---|
0331bbf3 NF |
1 | * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) |
2 | ||
3 | Required properties: | |
8c07f664 | 4 | - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu" |
0331bbf3 NF |
5 | The compatible <chip> indicated will be the first SoC to support an |
6 | additional mode or an USART new feature. | |
8c07f664 | 7 | For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart" |
0331bbf3 NF |
8 | - reg: Should contain registers location and length |
9 | - interrupts: Should contain interrupt | |
8be3da65 BB |
10 | - clock-names: tuple listing input clock names. |
11 | Required elements: "usart" | |
12 | - clocks: phandles to input clocks. | |
0331bbf3 NF |
13 | |
14 | Optional properties: | |
15 | - atmel,use-dma-rx: use of PDC or DMA for receiving data | |
16 | - atmel,use-dma-tx: use of PDC or DMA for transmitting data | |
e0b0baad RG |
17 | - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. |
18 | It will use specified PIO instead of the peripheral function pin for the USART feature. | |
19 | If unsure, don't specify this property. | |
e4697193 ES |
20 | - add dma bindings for dma transfer: |
21 | - dmas: DMA specifier, consisting of a phandle to DMA controller node, | |
22 | memory peripheral interface and USART DMA channel ID, FIFO configuration. | |
23 | Refer to dma.txt and atmel-dma.txt for details. | |
24 | - dma-names: "rx" for RX channel, "tx" for TX channel. | |
05a05143 CP |
25 | - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO |
26 | capable USARTs. | |
0331bbf3 NF |
27 | |
28 | <chip> compatible description: | |
29 | - at91rm9200: legacy USART support | |
30 | - at91sam9260: generic USART implementation for SAM9 SoCs | |
31 | ||
32 | Example: | |
e4697193 | 33 | - use PDC: |
0331bbf3 NF |
34 | usart0: serial@fff8c000 { |
35 | compatible = "atmel,at91sam9260-usart"; | |
36 | reg = <0xfff8c000 0x4000>; | |
37 | interrupts = <7>; | |
8be3da65 BB |
38 | clocks = <&usart0_clk>; |
39 | clock-names = "usart"; | |
0331bbf3 NF |
40 | atmel,use-dma-rx; |
41 | atmel,use-dma-tx; | |
7f40605a | 42 | rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; |
e0b0baad RG |
43 | cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; |
44 | dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; | |
45 | dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; | |
46 | dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; | |
47 | rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; | |
0331bbf3 NF |
48 | }; |
49 | ||
e4697193 ES |
50 | - use DMA: |
51 | usart0: serial@f001c000 { | |
52 | compatible = "atmel,at91sam9260-usart"; | |
53 | reg = <0xf001c000 0x100>; | |
54 | interrupts = <12 4 5>; | |
8be3da65 BB |
55 | clocks = <&usart0_clk>; |
56 | clock-names = "usart"; | |
e4697193 ES |
57 | atmel,use-dma-rx; |
58 | atmel,use-dma-tx; | |
59 | dmas = <&dma0 2 0x3>, | |
60 | <&dma0 2 0x204>; | |
61 | dma-names = "tx", "rx"; | |
05a05143 | 62 | atmel,fifo-size = <32>; |
e4697193 | 63 | }; |