Commit | Line | Data |
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a6e56c28 DM |
1 | Device tree bindings for Marvell PXA SSP ports |
2 | ||
3 | Required properties: | |
4 | ||
5 | - compatible: Must be one of | |
6 | mrvl,pxa25x-ssp | |
7 | mvrl,pxa25x-nssp | |
8 | mrvl,pxa27x-ssp | |
9 | mrvl,pxa3xx-ssp | |
10 | mvrl,pxa168-ssp | |
11 | mrvl,pxa910-ssp | |
12 | mrvl,ce4100-ssp | |
13 | mrvl,lpss-ssp | |
14 | ||
15 | - reg: The memory base | |
16 | - dmas: Two dma phandles, one for rx, one for tx | |
17 | - dma-names: Must be "rx", "tx" | |
18 | ||
19 | ||
20 | Example for PXA3xx: | |
21 | ||
22 | ssp0: ssp@41000000 { | |
23 | compatible = "mrvl,pxa3xx-ssp"; | |
24 | reg = <0x41000000 0x40>; | |
25 | ssp-id = <1>; | |
26 | interrupts = <24>; | |
27 | clock-names = "pxa27x-ssp.0"; | |
28 | dmas = <&dma 13 | |
29 | &dma 14>; | |
30 | dma-names = "rx", "tx"; | |
31 | }; | |
32 | ||
33 | ssp1: ssp@41700000 { | |
34 | compatible = "mrvl,pxa3xx-ssp"; | |
35 | reg = <0x41700000 0x40>; | |
36 | ssp-id = <2>; | |
37 | interrupts = <16>; | |
38 | clock-names = "pxa27x-ssp.1"; | |
39 | dmas = <&dma 15 | |
40 | &dma 16>; | |
41 | dma-names = "rx", "tx"; | |
42 | }; | |
43 | ||
44 | ssp2: ssp@41900000 { | |
45 | compatibl3 = "mrvl,pxa3xx-ssp"; | |
46 | reg = <0x41900000 0x40>; | |
47 | ssp-id = <3>; | |
48 | interrupts = <0>; | |
49 | clock-names = "pxa27x-ssp.2"; | |
50 | dmas = <&dma 66 | |
51 | &dma 67>; | |
52 | dma-names = "rx", "tx"; | |
53 | }; | |
54 | ||
55 | ssp3: ssp@41a00000 { | |
56 | compatible = "mrvl,pxa3xx-ssp"; | |
57 | reg = <0x41a00000 0x40>; | |
58 | ssp-id = <4>; | |
59 | interrupts = <13>; | |
60 | clock-names = "pxa27x-ssp.3"; | |
61 | dmas = <&dma 2 | |
62 | &dma 3>; | |
63 | dma-names = "rx", "tx"; | |
64 | }; | |
65 |