Commit | Line | Data |
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e9ea096d LD |
1 | NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. |
2 | ||
3 | Required properties: | |
4 | - compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". | |
5 | - reg: Should contain UART controller registers location and length. | |
6 | - interrupts: Should contain UART controller interrupts. | |
d8f64797 SW |
7 | - clocks: Must contain one entry, for the module clock. |
8 | See ../clocks/clock-bindings.txt for details. | |
07999587 SW |
9 | - resets : Must contain an entry for each entry in reset-names. |
10 | See ../reset/reset.txt for details. | |
11 | - reset-names : Must include the following entries: | |
12 | - serial | |
ed520c90 SW |
13 | - dmas : Must contain an entry for each entry in clock-names. |
14 | See ../dma/dma.txt for details. | |
15 | - dma-names : Must include the following entries: | |
16 | - rx | |
17 | - tx | |
e9ea096d LD |
18 | |
19 | Optional properties: | |
20 | - nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable | |
21 | only if all 8 lines of UART controller are pinmuxed. | |
22 | ||
23 | Example: | |
24 | ||
25 | serial@70006000 { | |
26 | compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; | |
27 | reg = <0x70006000 0x40>; | |
28 | reg-shift = <2>; | |
29 | interrupts = <0 36 0x04>; | |
e9ea096d | 30 | nvidia,enable-modem-interrupt; |
d8f64797 | 31 | clocks = <&tegra_car 6>; |
07999587 SW |
32 | resets = <&tegra_car 6>; |
33 | reset-names = "serial"; | |
ed520c90 SW |
34 | dmas = <&apbdma 8>, <&apbdma 8>; |
35 | dma-names = "rx", "tx"; | |
e9ea096d LD |
36 | status = "disabled"; |
37 | }; |