Commit | Line | Data |
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787b0c1f AB |
1 | * ARM AMBA Primecell PL011 serial UART |
2 | ||
3 | Required properties: | |
4 | - compatible: must be "arm,primecell", "arm,pl011" | |
5 | - reg: exactly one register range with length 0x1000 | |
6 | - interrupts: exactly one interrupt specifier | |
7 | ||
8 | Optional properties: | |
a81a6c65 LW |
9 | - pinctrl: When present, must have one state named "default", |
10 | and may contain a second name named "sleep". The former | |
11 | state sets up pins for ordinary operation whereas | |
12 | the latter state will put the associated pins to sleep | |
13 | when the UART is unused | |
14 | - clocks: When present, the first clock listed must correspond to | |
15 | the clock named UARTCLK on the IP block, i.e. the clock | |
16 | to the external serial line, whereas the second clock | |
17 | must correspond to the PCLK clocking the internal logic | |
18 | of the block. Just listing one clock (the first one) is | |
19 | deprecated. | |
20 | - clocks-names: When present, the first clock listed must be named | |
21 | "uartclk" and the second clock listed must be named | |
787b0c1f AB |
22 | "apb_pclk" |
23 | - dmas: When present, may have one or two dma channels. | |
24 | The first one must be named "rx", the second one | |
25 | must be named "tx". | |
26 | ||
27 | See also bindings/arm/primecell.txt | |
a81a6c65 LW |
28 | |
29 | Example: | |
30 | ||
31 | uart@80120000 { | |
32 | compatible = "arm,pl011", "arm,primecell"; | |
33 | reg = <0x80120000 0x1000>; | |
34 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; | |
35 | dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; | |
36 | dma-names = "rx", "tx"; | |
37 | clocks = <&foo_clk>, <&bar_clk>; | |
38 | clock-names = "uartclk", "apb_pclk"; | |
39 | }; |