Commit | Line | Data |
---|---|---|
dd910d98 GJ |
1 | * Qualcomm Atheros AR9330 High-Speed UART |
2 | ||
3 | Required properties: | |
4 | ||
5 | - compatible: Must be "qca,ar9330-uart" | |
6 | ||
7 | - reg: Specifies the physical base address of the controller and | |
8 | the length of the memory mapped region. | |
9 | ||
10 | - interrupt-parent: The phandle for the interrupt controller that | |
11 | services interrupts for this device. | |
12 | ||
13 | - interrupts: Specifies the interrupt source of the parent interrupt | |
14 | controller. The format of the interrupt specifier depends on the | |
15 | parent interrupt controller. | |
16 | ||
17 | Additional requirements: | |
18 | ||
19 | Each UART port must have an alias correctly numbered in "aliases" | |
20 | node. | |
21 | ||
22 | Example: | |
23 | ||
24 | aliases { | |
25 | serial0 = &uart0; | |
26 | }; | |
27 | ||
28 | uart0: uart@18020000 { | |
29 | compatible = "qca,ar9330-uart"; | |
30 | reg = <0x18020000 0x14>; | |
31 | ||
32 | interrupt-parent = <&intc>; | |
33 | interrupts = <3>; | |
34 | }; |