Commit | Line | Data |
---|---|---|
6e01365c SB |
1 | * MSM Serial UARTDM |
2 | ||
3 | The MSM serial UARTDM hardware is designed for high-speed use cases where the | |
4 | transmit and/or receive channels can be offloaded to a dma-engine. From a | |
5 | software perspective it's mostly compatible with the MSM serial UART except | |
6 | that it supports reading and writing multiple characters at a time. | |
7 | ||
8 | Required properties: | |
9 | - compatible: Should contain at least "qcom,msm-uartdm". | |
10 | A more specific property should be specified as follows depending | |
11 | on the version: | |
12 | "qcom,msm-uartdm-v1.1" | |
13 | "qcom,msm-uartdm-v1.2" | |
14 | "qcom,msm-uartdm-v1.3" | |
15 | "qcom,msm-uartdm-v1.4" | |
16 | - reg: Should contain UART register locations and lengths. The first | |
17 | register shall specify the main control registers. An optional second | |
18 | register location shall specify the GSBI control region. | |
19 | "qcom,msm-uartdm-v1.3" is the only compatible value that might | |
20 | need the GSBI control region. | |
21 | - interrupts: Should contain UART interrupt. | |
22 | - clocks: Should contain the core clock and the AHB clock. | |
23 | - clock-names: Should be "core" for the core clock and "iface" for the | |
24 | AHB clock. | |
25 | ||
26 | Optional properties: | |
27 | - dmas: Should contain dma specifiers for transmit and receive channels | |
28 | - dma-names: Should contain "tx" for transmit and "rx" for receive channels | |
29 | ||
30 | Examples: | |
31 | ||
32 | A uartdm v1.4 device with dma capabilities. | |
33 | ||
34 | serial@f991e000 { | |
35 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
36 | reg = <0xf991e000 0x1000>; | |
37 | interrupts = <0 108 0x0>; | |
38 | clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; | |
39 | clock-names = "core", "iface"; | |
40 | dmas = <&dma0 0>, <&dma0 1>; | |
41 | dma-names = "tx", "rx"; | |
42 | }; | |
43 | ||
44 | A uartdm v1.3 device without dma capabilities and part of a GSBI complex. | |
45 | ||
46 | serial@19c40000 { | |
47 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
48 | reg = <0x19c40000 0x1000>, | |
49 | <0x19c00000 0x1000>; | |
50 | interrupts = <0 195 0x0>; | |
51 | clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; | |
52 | clock-names = "core", "iface"; | |
53 | }; |