[deliverable/linux.git] / Documentation / devicetree / bindings / sound / fsl,spdif.txt

Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller

The Freescale S/PDIF audio block is a stereo transceiver that allows the
processor to receive and transmit digital audio via an coaxial cable or
a fibre cable.

Required properties:

  - compatible		: Compatible list, must contain "fsl,imx35-spdif".

  - reg			: Offset and length of the register set for the device.

  - interrupts		: Contains the spdif interrupt.

  - dmas		: Generic dma devicetree binding as described in
			  Documentation/devicetree/bindings/dma/dma.txt.

  - dma-names		: Two dmas have to be defined, "tx" and "rx".

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:
	"core"		  The core clock of spdif controller.
	"rxtx<0-7>"	  Clock source list for tx and rx clock.
			  This clock list should be identical to the source
			  list connecting to the spdif clock mux in "SPDIF
			  Transceiver Clock Diagram" of SoC reference manual.
			  It can also be referred to TxClk_Source bit of
			  register SPDIF_STC.

   - big-endian		: If this property is absent, the native endian mode
			  will be in use as default, or the big endian mode
			  will be in use for all the device registers.

Example:

spdif: spdif@02004000 {
	compatible = "fsl,imx35-spdif";
	reg = <0x02004000 0x4000>;
	interrupts = <0 52 0x04>;
	dmas = <&sdma 14 18 0>,
	       <&sdma 15 18 0>;
	dma-names = "rx", "tx";

	clocks = <&clks 197>, <&clks 3>,
	       <&clks 197>, <&clks 107>,
	       <&clks 0>, <&clks 118>,
	       <&clks 62>, <&clks 139>,
	       <&clks 0>;
	clock-names = "core", "rxtx0",
		"rxtx1", "rxtx2",
		"rxtx3", "rxtx4",
		"rxtx5", "rxtx6",
		"rxtx7";

	big-endian;
	status = "okay";
};
Commit	Line	Data
a2388a49 NC	1	Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
	2
	3	The Freescale S/PDIF audio block is a stereo transceiver that allows the
	4	processor to receive and transmit digital audio via an coaxial cable or
	5	a fibre cable.
	6
	7	Required properties:
	8
9c4c1045	9	- compatible : Compatible list, must contain "fsl,imx35-spdif".
a2388a49	10
9c4c1045	11	- reg : Offset and length of the register set for the device.
a2388a49	12
9c4c1045	13	- interrupts : Contains the spdif interrupt.
a2388a49	14
9c4c1045 NC	15	- dmas : Generic dma devicetree binding as described in
9c4c1045 NC	16	Documentation/devicetree/bindings/dma/dma.txt.
a2388a49	17
9c4c1045	18	- dma-names : Two dmas have to be defined, "tx" and "rx".
a2388a49	19
9c4c1045	20	- clocks : Contains an entry for each entry in clock-names.
a2388a49	21
9c4c1045 NC	22	- clock-names : Includes the following entries:
	23	"core" The core clock of spdif controller.
	24	"rxtx<0-7>" Clock source list for tx and rx clock.
	25	This clock list should be identical to the source
	26	list connecting to the spdif clock mux in "SPDIF
	27	Transceiver Clock Diagram" of SoC reference manual.
	28	It can also be referred to TxClk_Source bit of
	29	register SPDIF_STC.
a2388a49	30
9c4c1045 NC	31	- big-endian : If this property is absent, the native endian mode
	32	will be in use as default, or the big endian mode
	33	will be in use for all the device registers.
86f28d76	34
a2388a49 NC	35	Example:
	36
	37	spdif: spdif@02004000 {
	38	compatible = "fsl,imx35-spdif";
	39	reg = <0x02004000 0x4000>;
	40	interrupts = <0 52 0x04>;
	41	dmas = <&sdma 14 18 0>,
	42	<&sdma 15 18 0>;
	43	dma-names = "rx", "tx";
	44
	45	clocks = <&clks 197>, <&clks 3>,
	46	<&clks 197>, <&clks 107>,
	47	<&clks 0>, <&clks 118>,
	48	<&clks 62>, <&clks 139>,
	49	<&clks 0>;
	50	clock-names = "core", "rxtx0",
	51	"rxtx1", "rxtx2",
	52	"rxtx3", "rxtx4",
	53	"rxtx5", "rxtx6",
	54	"rxtx7";
	55
86f28d76	56	big-endian;
a2388a49 NC	57	status = "okay";
a2388a49 NC	58	};