Commit | Line | Data |
---|---|---|
a2388a49 NC |
1 | Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller |
2 | ||
3 | The Freescale S/PDIF audio block is a stereo transceiver that allows the | |
4 | processor to receive and transmit digital audio via an coaxial cable or | |
5 | a fibre cable. | |
6 | ||
7 | Required properties: | |
8 | ||
9 | - compatible : Compatible list, must contain "fsl,imx35-spdif". | |
10 | ||
11 | - reg : Offset and length of the register set for the device. | |
12 | ||
13 | - interrupts : Contains the spdif interrupt. | |
14 | ||
15 | - dmas : Generic dma devicetree binding as described in | |
16 | Documentation/devicetree/bindings/dma/dma.txt. | |
17 | ||
18 | - dma-names : Two dmas have to be defined, "tx" and "rx". | |
19 | ||
20 | - clocks : Contains an entry for each entry in clock-names. | |
21 | ||
22 | - clock-names : Includes the following entries: | |
23 | "core" The core clock of spdif controller | |
24 | "rxtx<0-7>" Clock source list for tx and rx clock. | |
25 | This clock list should be identical to | |
26 | the source list connecting to the spdif | |
27 | clock mux in "SPDIF Transceiver Clock | |
28 | Diagram" of SoC reference manual. It | |
29 | can also be referred to TxClk_Source | |
30 | bit of register SPDIF_STC. | |
31 | ||
32 | Example: | |
33 | ||
34 | spdif: spdif@02004000 { | |
35 | compatible = "fsl,imx35-spdif"; | |
36 | reg = <0x02004000 0x4000>; | |
37 | interrupts = <0 52 0x04>; | |
38 | dmas = <&sdma 14 18 0>, | |
39 | <&sdma 15 18 0>; | |
40 | dma-names = "rx", "tx"; | |
41 | ||
42 | clocks = <&clks 197>, <&clks 3>, | |
43 | <&clks 197>, <&clks 107>, | |
44 | <&clks 0>, <&clks 118>, | |
45 | <&clks 62>, <&clks 139>, | |
46 | <&clks 0>; | |
47 | clock-names = "core", "rxtx0", | |
48 | "rxtx1", "rxtx2", | |
49 | "rxtx3", "rxtx4", | |
50 | "rxtx5", "rxtx6", | |
51 | "rxtx7"; | |
52 | ||
53 | status = "okay"; | |
54 | }; |