Commit | Line | Data |
---|---|---|
a2388a49 NC |
1 | Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller |
2 | ||
3 | The Freescale S/PDIF audio block is a stereo transceiver that allows the | |
4 | processor to receive and transmit digital audio via an coaxial cable or | |
5 | a fibre cable. | |
6 | ||
7 | Required properties: | |
8 | ||
9c4c1045 | 9 | - compatible : Compatible list, must contain "fsl,imx35-spdif". |
a2388a49 | 10 | |
9c4c1045 | 11 | - reg : Offset and length of the register set for the device. |
a2388a49 | 12 | |
9c4c1045 | 13 | - interrupts : Contains the spdif interrupt. |
a2388a49 | 14 | |
9c4c1045 NC |
15 | - dmas : Generic dma devicetree binding as described in |
16 | Documentation/devicetree/bindings/dma/dma.txt. | |
a2388a49 | 17 | |
9c4c1045 | 18 | - dma-names : Two dmas have to be defined, "tx" and "rx". |
a2388a49 | 19 | |
9c4c1045 | 20 | - clocks : Contains an entry for each entry in clock-names. |
a2388a49 | 21 | |
9c4c1045 NC |
22 | - clock-names : Includes the following entries: |
23 | "core" The core clock of spdif controller. | |
24 | "rxtx<0-7>" Clock source list for tx and rx clock. | |
25 | This clock list should be identical to the source | |
26 | list connecting to the spdif clock mux in "SPDIF | |
27 | Transceiver Clock Diagram" of SoC reference manual. | |
28 | It can also be referred to TxClk_Source bit of | |
29 | register SPDIF_STC. | |
0bc5680a SW |
30 | "spba" The spba clock is required when SPDIF is placed as a |
31 | bus slave of the Shared Peripheral Bus and when two | |
32 | or more bus masters (CPU, DMA or DSP) try to access | |
33 | it. This property is optional depending on the SoC | |
34 | design. | |
a2388a49 | 35 | |
9c4c1045 NC |
36 | - big-endian : If this property is absent, the native endian mode |
37 | will be in use as default, or the big endian mode | |
38 | will be in use for all the device registers. | |
86f28d76 | 39 | |
a2388a49 NC |
40 | Example: |
41 | ||
42 | spdif: spdif@02004000 { | |
43 | compatible = "fsl,imx35-spdif"; | |
44 | reg = <0x02004000 0x4000>; | |
45 | interrupts = <0 52 0x04>; | |
46 | dmas = <&sdma 14 18 0>, | |
47 | <&sdma 15 18 0>; | |
48 | dma-names = "rx", "tx"; | |
49 | ||
50 | clocks = <&clks 197>, <&clks 3>, | |
51 | <&clks 197>, <&clks 107>, | |
52 | <&clks 0>, <&clks 118>, | |
53 | <&clks 62>, <&clks 139>, | |
54 | <&clks 0>; | |
55 | clock-names = "core", "rxtx0", | |
56 | "rxtx1", "rxtx2", | |
57 | "rxtx3", "rxtx4", | |
58 | "rxtx5", "rxtx6", | |
59 | "rxtx7"; | |
60 | ||
86f28d76 | 61 | big-endian; |
a2388a49 NC |
62 | status = "okay"; |
63 | }; |