Commit | Line | Data |
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d0fc2eaa KG |
1 | Freescale Synchronous Serial Interface |
2 | ||
3 | The SSI is a serial device that communicates with audio codecs. It can | |
4 | be programmed in AC97, I2S, left-justified, or right-justified modes. | |
5 | ||
6 | Required properties: | |
10901e53 MP |
7 | - compatible: Compatible list, should contain one of the following |
8 | compatibles: | |
9 | fsl,mpc8610-ssi | |
10 | fsl,imx51-ssi | |
11 | fsl,imx35-ssi | |
12 | fsl,imx21-ssi | |
df4b6806 TT |
13 | - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on. |
14 | - reg: Offset and length of the register set for the device. | |
15 | - interrupts: <a b> where a is the interrupt number and b is a | |
16 | field that represents an encoding of the sense and | |
17 | level information for the interrupt. This should be | |
18 | encoded based on the information in section 2) | |
19 | depending on the type of interrupt controller you | |
20 | have. | |
21 | - interrupt-parent: The phandle for the interrupt controller that | |
22 | services interrupts for this device. | |
df4b6806 | 23 | - fsl,playback-dma: Phandle to a node for the DMA channel to use for |
b56c2768 TT |
24 | playback of audio. This is typically dictated by SOC |
25 | design. See the notes below. | |
df4b6806 | 26 | - fsl,capture-dma: Phandle to a node for the DMA channel to use for |
b56c2768 TT |
27 | capture (recording) of audio. This is typically dictated |
28 | by SOC design. See the notes below. | |
df4b6806 | 29 | - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. |
0bcd783c | 30 | This number is the maximum allowed value for SFCSR[TFWM0]. |
df4b6806 TT |
31 | - fsl,ssi-asynchronous: |
32 | If specified, the SSI is to be programmed in asynchronous | |
33 | mode. In this mode, pins SRCK, STCK, SRFS, and STFS must | |
34 | all be connected to valid signals. In synchronous mode, | |
35 | SRCK and SRFS are ignored. Asynchronous mode allows | |
36 | playback and capture to use different sample sizes and | |
37 | sample rates. Some drivers may require that SRCK and STCK | |
38 | be connected together, and SRFS and STFS be connected | |
39 | together. This would still allow different sample sizes, | |
40 | but not different sample rates. | |
3567de67 MP |
41 | - clocks: "ipg" - Required clock for the SSI unit |
42 | "baud" - Required clock for SSI master mode. Otherwise this | |
43 | clock is not used | |
d0fc2eaa | 44 | |
cd7f0295 MP |
45 | Required are also ac97 link bindings if ac97 is used. See |
46 | Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary | |
47 | bindings. | |
48 | ||
d0fc2eaa | 49 | Optional properties: |
df4b6806 TT |
50 | - codec-handle: Phandle to a 'codec' node that defines an audio |
51 | codec connected to this SSI. This node is typically | |
52 | a child of an I2C or other control node. | |
de623ece MP |
53 | - fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to |
54 | filter the codec stream. This is necessary for some boards | |
55 | where an incompatible codec is connected to this SSI, e.g. | |
56 | on pca100 and pcm043. | |
3a5e517b MP |
57 | - dmas: Generic dma devicetree binding as described in |
58 | Documentation/devicetree/bindings/dma/dma.txt. | |
59 | - dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq | |
60 | is not defined. | |
b93427b1 | 61 | - fsl,mode: The operating mode for the AC97 interface only. |
3567de67 MP |
62 | "ac97-slave" - AC97 mode, SSI is clock slave |
63 | "ac97-master" - AC97 mode, SSI is clock master | |
d0fc2eaa KG |
64 | |
65 | Child 'codec' node required properties: | |
df4b6806 | 66 | - compatible: Compatible list, contains the name of the codec |
d0fc2eaa KG |
67 | |
68 | Child 'codec' node optional properties: | |
df4b6806 TT |
69 | - clock-frequency: The frequency of the input clock, which typically comes |
70 | from an on-board dedicated oscillator. | |
c2fe5944 TT |
71 | |
72 | Notes on fsl,playback-dma and fsl,capture-dma: | |
73 | ||
74 | On SOCs that have an SSI, specific DMA channels are hard-wired for playback | |
75 | and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for | |
76 | playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for | |
77 | playback and DMA channel 3 for capture. The developer can choose which | |
78 | DMA controller to use, but the channels themselves are hard-wired. The | |
79 | purpose of these two properties is to represent this hardware design. | |
b56c2768 TT |
80 | |
81 | The device tree nodes for the DMA channels that are referenced by | |
82 | "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with | |
83 | "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g. | |
84 | "fsl,mpc8610-dma-channel") can remain. If these nodes are left as | |
85 | "fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA | |
86 | drivers (fsldma) will attempt to use them, and it will conflict with the | |
87 | sound drivers. |