Commit | Line | Data |
---|---|---|
d3986650 GT |
1 | Mediatek AFE PCM controller for mt2701 |
2 | ||
3 | Required properties: | |
4 | - compatible = "mediatek,mt2701-audio"; | |
5 | - reg: register location and size | |
6 | - interrupts: Should contain AFE interrupt | |
7 | - clock-names: should have these clock names: | |
8 | "infra_sys_audio_clk", | |
9 | "top_audio_mux1_sel", | |
10 | "top_audio_mux2_sel", | |
11 | "top_audio_mux1_div", | |
12 | "top_audio_mux2_div", | |
13 | "top_audio_48k_timing", | |
14 | "top_audio_44k_timing", | |
15 | "top_audpll_mux_sel", | |
16 | "top_apll_sel", | |
17 | "top_aud1_pll_98M", | |
18 | "top_aud2_pll_90M", | |
19 | "top_hadds2_pll_98M", | |
20 | "top_hadds2_pll_294M", | |
21 | "top_audpll", | |
22 | "top_audpll_d4", | |
23 | "top_audpll_d8", | |
24 | "top_audpll_d16", | |
25 | "top_audpll_d24", | |
26 | "top_audintbus_sel", | |
27 | "clk_26m", | |
28 | "top_syspll1_d4", | |
29 | "top_aud_k1_src_sel", | |
30 | "top_aud_k2_src_sel", | |
31 | "top_aud_k3_src_sel", | |
32 | "top_aud_k4_src_sel", | |
33 | "top_aud_k5_src_sel", | |
34 | "top_aud_k6_src_sel", | |
35 | "top_aud_k1_src_div", | |
36 | "top_aud_k2_src_div", | |
37 | "top_aud_k3_src_div", | |
38 | "top_aud_k4_src_div", | |
39 | "top_aud_k5_src_div", | |
40 | "top_aud_k6_src_div", | |
41 | "top_aud_i2s1_mclk", | |
42 | "top_aud_i2s2_mclk", | |
43 | "top_aud_i2s3_mclk", | |
44 | "top_aud_i2s4_mclk", | |
45 | "top_aud_i2s5_mclk", | |
46 | "top_aud_i2s6_mclk", | |
47 | "top_asm_m_sel", | |
48 | "top_asm_h_sel", | |
49 | "top_univpll2_d4", | |
50 | "top_univpll2_d2", | |
51 | "top_syspll_d5"; | |
52 | ||
53 | Example: | |
54 | ||
55 | afe: mt2701-afe-pcm@11220000 { | |
56 | compatible = "mediatek,mt2701-audio"; | |
57 | reg = <0 0x11220000 0 0x2000>, | |
58 | <0 0x112A0000 0 0x20000>; | |
59 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, | |
60 | <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; | |
61 | clocks = <&infracfg CLK_INFRA_AUDIO>, | |
62 | <&topckgen CLK_TOP_AUD_MUX1_SEL>, | |
63 | <&topckgen CLK_TOP_AUD_MUX2_SEL>, | |
64 | <&topckgen CLK_TOP_AUD_MUX1_DIV>, | |
65 | <&topckgen CLK_TOP_AUD_MUX2_DIV>, | |
66 | <&topckgen CLK_TOP_AUD_48K_TIMING>, | |
67 | <&topckgen CLK_TOP_AUD_44K_TIMING>, | |
68 | <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, | |
69 | <&topckgen CLK_TOP_APLL_SEL>, | |
70 | <&topckgen CLK_TOP_AUD1PLL_98M>, | |
71 | <&topckgen CLK_TOP_AUD2PLL_90M>, | |
72 | <&topckgen CLK_TOP_HADDS2PLL_98M>, | |
73 | <&topckgen CLK_TOP_HADDS2PLL_294M>, | |
74 | <&topckgen CLK_TOP_AUDPLL>, | |
75 | <&topckgen CLK_TOP_AUDPLL_D4>, | |
76 | <&topckgen CLK_TOP_AUDPLL_D8>, | |
77 | <&topckgen CLK_TOP_AUDPLL_D16>, | |
78 | <&topckgen CLK_TOP_AUDPLL_D24>, | |
79 | <&topckgen CLK_TOP_AUDINTBUS_SEL>, | |
80 | <&clk26m>, | |
81 | <&topckgen CLK_TOP_SYSPLL1_D4>, | |
82 | <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, | |
83 | <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, | |
84 | <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, | |
85 | <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, | |
86 | <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, | |
87 | <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, | |
88 | <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, | |
89 | <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, | |
90 | <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, | |
91 | <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, | |
92 | <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, | |
93 | <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, | |
94 | <&topckgen CLK_TOP_AUD_I2S1_MCLK>, | |
95 | <&topckgen CLK_TOP_AUD_I2S2_MCLK>, | |
96 | <&topckgen CLK_TOP_AUD_I2S3_MCLK>, | |
97 | <&topckgen CLK_TOP_AUD_I2S4_MCLK>, | |
98 | <&topckgen CLK_TOP_AUD_I2S5_MCLK>, | |
99 | <&topckgen CLK_TOP_AUD_I2S6_MCLK>, | |
100 | <&topckgen CLK_TOP_ASM_M_SEL>, | |
101 | <&topckgen CLK_TOP_ASM_H_SEL>, | |
102 | <&topckgen CLK_TOP_UNIVPLL2_D4>, | |
103 | <&topckgen CLK_TOP_UNIVPLL2_D2>, | |
104 | <&topckgen CLK_TOP_SYSPLL_D5>; | |
105 | ||
106 | clock-names = "infra_sys_audio_clk", | |
107 | "top_audio_mux1_sel", | |
108 | "top_audio_mux2_sel", | |
109 | "top_audio_mux1_div", | |
110 | "top_audio_mux2_div", | |
111 | "top_audio_48k_timing", | |
112 | "top_audio_44k_timing", | |
113 | "top_audpll_mux_sel", | |
114 | "top_apll_sel", | |
115 | "top_aud1_pll_98M", | |
116 | "top_aud2_pll_90M", | |
117 | "top_hadds2_pll_98M", | |
118 | "top_hadds2_pll_294M", | |
119 | "top_audpll", | |
120 | "top_audpll_d4", | |
121 | "top_audpll_d8", | |
122 | "top_audpll_d16", | |
123 | "top_audpll_d24", | |
124 | "top_audintbus_sel", | |
125 | "clk_26m", | |
126 | "top_syspll1_d4", | |
127 | "top_aud_k1_src_sel", | |
128 | "top_aud_k2_src_sel", | |
129 | "top_aud_k3_src_sel", | |
130 | "top_aud_k4_src_sel", | |
131 | "top_aud_k5_src_sel", | |
132 | "top_aud_k6_src_sel", | |
133 | "top_aud_k1_src_div", | |
134 | "top_aud_k2_src_div", | |
135 | "top_aud_k3_src_div", | |
136 | "top_aud_k4_src_div", | |
137 | "top_aud_k5_src_div", | |
138 | "top_aud_k6_src_div", | |
139 | "top_aud_i2s1_mclk", | |
140 | "top_aud_i2s2_mclk", | |
141 | "top_aud_i2s3_mclk", | |
142 | "top_aud_i2s4_mclk", | |
143 | "top_aud_i2s5_mclk", | |
144 | "top_aud_i2s6_mclk", | |
145 | "top_asm_m_sel", | |
146 | "top_asm_h_sel", | |
147 | "top_univpll2_d4", | |
148 | "top_univpll2_d2", | |
149 | "top_syspll_d5"; | |
150 | }; |